CN300/STU/src_middlewares/stm32f1xx_STUperipheralRegisters.c

#include "stm32f1xx_STUperipheralRegisters.h"
#include "stm32fxx_STUlib.h"
#include "var.h"

#define TEST_DATA_32B_0X55  0x55555555
#define TEST_DATA_32B_0XAA	0xAAAAAAAA

uint8_t GPIO_register_selftest(GPIO_TypeDef* GPIOx);
uint8_t AFIO_register_selftest(AFIO_TypeDef* AFIOx);
uint8_t CAN_register_selftest(CAN_TypeDef* CANx);
uint8_t DMA_Channel_selftest(DMA_Channel_TypeDef* DMA);
uint8_t ADC_register_selftest(ADC_TypeDef* ADCx);
uint8_t TIM_register_selftest(TIM_TypeDef* TIMx);

void STU_delay_us(uint16_t time)
{    
   uint16_t i=0;  
   while(time--)
   {
      i=7;  //72MHZ主频，1us
      while(i--) ;    
   }
}

uint8_t STU_PeripheralRegistersTest(void)
{
	//uint8_t result;
	
	/*********************** GPIO registers test*******************/
	__HAL_RCC_GPIOA_CLK_ENABLE();
	__HAL_RCC_GPIOB_CLK_ENABLE();
	__HAL_RCC_GPIOC_CLK_ENABLE();
	__HAL_RCC_GPIOD_CLK_ENABLE();
	
	if(GPIO_register_selftest(GPIOA) == ERROR )
	{
		return ERROR;
	}
	if(GPIO_register_selftest(GPIOB) == ERROR )
	{
		return ERROR;
	}
	if(GPIO_register_selftest(GPIOC) == ERROR )
	{
		return ERROR;
	}
	if(GPIO_register_selftest(GPIOD) == ERROR )
	{
		return ERROR;
	}

	__HAL_RCC_GPIOA_CLK_DISABLE();
	__HAL_RCC_GPIOB_CLK_DISABLE();
	__HAL_RCC_GPIOC_CLK_DISABLE();
	__HAL_RCC_GPIOD_CLK_DISABLE();
	
	AFIO_register_selftest(AFIO);
	
	/*********************** CAN registers test*******************/
//	__HAL_RCC_CAN1_CLK_ENABLE();
//	if(CAN_register_selftest(CAN1) == ERROR)
//	{
//		return ERROR;
//	}
//	__HAL_RCC_CAN1_CLK_DISABLE();
	
	/*********************** DMA registers test*******************/
	__HAL_RCC_DMA1_CLK_ENABLE();
	if(DMA_Channel_selftest(DMA1_Channel1) == ERROR)
	{
		return ERROR;
	}
	__HAL_RCC_DMA1_CLK_DISABLE();
	
	/*********************** ADC registers test*******************/
	__HAL_RCC_ADC1_CLK_ENABLE();
	__HAL_RCC_ADC2_CLK_ENABLE();   
	if(ADC_register_selftest(ADC1) == ERROR)
	{
		return ERROR;
	}
	if(ADC_register_selftest(ADC2) == ERROR)
	{
		return ERROR;
	}
	__HAL_RCC_ADC1_CLK_DISABLE();
	__HAL_RCC_ADC2_CLK_DISABLE();
	
	/*********************** TIM registers test*******************/
	__HAL_RCC_TIM1_CLK_ENABLE();
	if(TIM_register_selftest(TIM1) == ERROR)
	{
		return ERROR;
	}
	__HAL_RCC_TIM1_CLK_DISABLE();
	
	return SUCCESS;
}


uint8_t GPIO_register_selftest(GPIO_TypeDef* GPIOx)
{
	unsigned long val=0;
//	unsigned int  uint_val=0;
	GPIO_TypeDef GPIO_tmp;
	
	/*备份寄存器的复位默认值*/
	GPIO_tmp.CRL = GPIOx->CRL;
	GPIO_tmp.CRH = GPIOx->CRH;
	//GPIO_tmp.IDR = GPIOx->IDR;       //read only
	GPIO_tmp.ODR = GPIOx->ODR;
	//GPIO_tmp.BSRR = GPIOx->BSRR ;   //write only
	//GPIO_tmp.BRR = GPIOx->BRR;      //write only
	//GPIO_tmp.LCKR = GPIOx->LCKR;    //lock register,don't test
	
	if(GPIOx != GPIOD)
	{
		//////////CRL //////////////	
		GPIOx->CRL=TEST_DATA_32B_0X55;
		//GPIOx->CRL=0x55555554;
		val=GPIOx->CRL;
		if(val!=TEST_DATA_32B_0X55)
		{
			//FIT_testflag = 10;
			return  (0);
		}
					
		GPIOx->CRL=TEST_DATA_32B_0XAA;
		val=GPIOx->CRL;
		if(val!=TEST_DATA_32B_0XAA)
					return  (0);	
	///////////CRH/////////////////////			
		GPIOx->CRH=TEST_DATA_32B_0X55;
		val=GPIOx->CRH;
		if(val!=TEST_DATA_32B_0X55)
					return  (0);
		GPIOx->CRH=TEST_DATA_32B_0XAA;
		val=GPIOx->CRH;
		if(val!=TEST_DATA_32B_0XAA)
					return  (0);
	///////////ODR/////////////////////
		GPIOx->ODR=0x00005555;
		val=GPIOx->ODR;
		if((val& 0x0000FFFF)!=0x00005555)
					return  (0);
		GPIOx->ODR=0x0000AAAA;
		val=GPIOx->ODR;
		if((val& 0x0000FFFF)!=0x0000AAAA)
					return  (0);	
	}
	else
	{
  	//////////CRL //////////////	
		GPIOx->CRL=(GPIO_tmp.CRL&0xFFFFF000)|0x00000555;
		val=GPIOx->CRL;
		if( (val&0x00000FFF) !=0x00000555 )
		{
			return  (0);
		}				
		GPIOx->CRL=(GPIO_tmp.CRL&0xFFFFF000)|0x00000AAA;
		val=GPIOx->CRL;
		if( (val&0x00000FFF) !=0x00000AAA )
					return  (0);	
	  ///////////ODR/////////////////////
		GPIOx->ODR=(GPIO_tmp.ODR&0xFFFFFFF8)|0x00000007;
		val=GPIOx->ODR;
		if((val& 0x00000007)!=0x00000007)
					return  (0);
		GPIOx->ODR=(GPIO_tmp.ODR&0xFFFFFFF8)|0x00000000;
		val=GPIOx->ODR;
		if((val& 0x00000007)!=0x00000000)
					return  (0);	
	}

	/*恢复寄存器的复位默认值*/
	GPIOx->CRL = GPIO_tmp.CRL;
	GPIOx->CRH = GPIO_tmp.CRH;
	GPIOx->ODR = GPIO_tmp.ODR;
	
	return  (1);
}


uint8_t AFIO_register_selftest(AFIO_TypeDef* AFIOx)
{
	uint32_t val=0;
	AFIO_TypeDef AFIO_tmp;
	
	/*备份寄存器的复位默认值*/
	AFIO_tmp.EVCR = AFIOx->EVCR;
	AFIO_tmp.MAPR = AFIOx->MAPR;
	AFIO_tmp.EXTICR[0] = AFIOx->EXTICR[0] ;
	AFIO_tmp.EXTICR[1] = AFIOx->EXTICR[1] ;
	AFIO_tmp.EXTICR[2] = AFIOx->EXTICR[2] ;
	AFIO_tmp.EXTICR[3] = AFIOx->EXTICR[3] ;
	
	//////////EVCR//////////////	
	AFIOx->EVCR=0x00000055;
	val=AFIOx->EVCR;
	if(val!=0x00000055)
				return  (0);
	AFIOx->EVCR=0x000000AA;
	val=AFIOx->EVCR;
		if(val!=0x000000AA)
				return  (0);
	//////////MAPR //////////////	
	AFIOx->MAPR=0x00005555;
	val=AFIOx->MAPR;
	if(val!=0x00005555)
				return  (0);
	AFIOx->MAPR=0x0000AAAA;
	val=(AFIOx->MAPR)&0x0000AAAA;
		if(val!=0x0000AAAA)
				return  (0);
	//////////EXTICR[0] //////////////	
	AFIOx->EXTICR[0]=0x00005555;
	val=AFIOx->EXTICR[0];
	if(val!=0x00005555)
				return  (0);
	AFIOx->EXTICR[0]=0x00002AAA;
	val=AFIOx->EXTICR[0];
		if(val!=0x00002AAA)
				return  (0);		
	//////////EXTICR[1] //////////////	
	AFIOx->EXTICR[1]=0x00005555;
	val=AFIOx->EXTICR[1];
	if(val!=0x00005555)
				return  (0);
	AFIOx->EXTICR[1]=0x00002AAA;
	val=AFIOx->EXTICR[1];
		if(val!=0x00002AAA)
				return  (0);	
	//////////EXTICR[2] //////////////	
	AFIOx->EXTICR[2]=0x00005555;
	val=AFIOx->EXTICR[2];
	if(val!=0x00005555)
				return  (0);
	AFIOx->EXTICR[2]=0x00002AAA;
	val=AFIOx->EXTICR[2];
		if(val!=0x00002AAA)
				return  (0);	
	//////////EXTICR[3] //////////////	
	AFIOx->EXTICR[3]=0x00005555;
	val=AFIOx->EXTICR[3];
	if(val!=0x00005555)
				return  (0);
	AFIOx->EXTICR[3]=0x00002AAA;
	val=AFIOx->EXTICR[3];
		if(val!=0x00002AAA)
				return  (0);		
	
	/*恢复寄存器的复位默认值*/
	AFIOx->EVCR = AFIO_tmp.EVCR;
	AFIOx->MAPR = AFIO_tmp.MAPR;
	AFIOx->EXTICR[0] = AFIO_tmp.EXTICR[0] ;
	AFIOx->EXTICR[1] = AFIO_tmp.EXTICR[1] ;
	AFIOx->EXTICR[2] = AFIO_tmp.EXTICR[2] ;
	AFIOx->EXTICR[3] = AFIO_tmp.EXTICR[3]  ;		
		
	return  (1);
}


uint8_t CAN_register_selftest(CAN_TypeDef* CANx)
{
	unsigned long val=0;

	//unsigned int  uint_val=0;
	uint32_t tmp_CAN_IER,tmp_CAN_BTR;   //tmp_CAN_MCR
	//tmp_CAN_MCR = CANx->MCR;
	tmp_CAN_IER = CANx->IER;
//	tmp_CAN_ESR = CANx->ESR;
	tmp_CAN_BTR = CANx->BTR;
	
//////////MCR //////////////
	CANx->MCR=0x00000055;
	val=CANx->MCR;
	if(val!=0x00000055)
				return  (0);
	CANx->MCR=0x000000A8;
	val=CANx->MCR;
	val = val & 0x000000A8;
		if(val!=0x000000A8)
				return  (0);
					
///////////IER//////////////
	CANx->IER=0x00010555;
	val=CANx->IER;
	if(val!=0x00010555)
				return  (0);

	CANx->IER=0x00028A2A;
	val=CANx->IER;
		if(val!=0x00028A2A)
				return  (0);

/////////////ESR//////////////
//	CANx->ESR=0x00000050;
//	val=CANx->ESR;
//	if(val!=0x00000050)
//				return  (0);
//	CANx->ESR=0x00000020;
//	val=CANx->ESR;
//		if(val!=0x00000020)
//				return  (0);
///////////BTR//////////////
	CANx->MCR=0x01;
	CANx->BTR=0x41550155;
	val=CANx->BTR;
	if(val!=0x41550155)
				return  (0);
					
	CANx->BTR=0x822A02AA;
	val=CANx->BTR;
		if(val!=0x822A02AA)
				return  (0);
					
	CANx->IER = tmp_CAN_IER;
//	CANx->ESR = tmp_CAN_ESR;
	CANx->BTR = tmp_CAN_BTR;	
		
	CANx->MCR = 0x00008000;	  //复位MCR寄存器
		
	return  (1);

}	


uint8_t DMA_Channel_selftest(DMA_Channel_TypeDef* DMA_Channelx)
{
	unsigned long val=0;
	//unsigned int  uint_val=0;
	DMA_Channel_TypeDef DMA_Channelx_tmp;
	
	DMA_Channelx_tmp.CCR = DMA_Channelx->CCR;
	DMA_Channelx_tmp.CNDTR = DMA_Channelx->CNDTR;
	DMA_Channelx_tmp.CPAR = DMA_Channelx->CPAR;
	DMA_Channelx_tmp.CMAR = DMA_Channelx->CMAR;
	
	//////////CCR//////////////
	DMA_Channelx->CCR = 0x00000000;
	DMA_Channelx->CCR=0x00005555;
	val=DMA_Channelx->CCR;
	if(val!=0x00005555)
				return  (0);
	DMA_Channelx->CCR = 0x00000000;
	DMA_Channelx->CCR=0x00002AAA;
	val=DMA_Channelx->CCR;
		if(val!=0x00002AAA)
				return  (0);
	//////////CNDTR//////////////
	DMA_Channelx->CCR = 0x00000000;
	DMA_Channelx->CNDTR=0x00005555;
	STU_delay_us(5);
	val=DMA_Channelx->CNDTR;
	if(val!=0x00005555)
				return  (0);
	DMA_Channelx->CNDTR=0x0000AAAA;
	STU_delay_us(5);
	val=DMA_Channelx->CNDTR;
		if(val!=0x0000AAAA)
				return  (0);
	//////////CPAR//////////////
	DMA_Channelx->CPAR=TEST_DATA_32B_0X55;
	val=DMA_Channelx->CPAR;
	if(val!=TEST_DATA_32B_0X55)
				return  (0);
	DMA_Channelx->CPAR=TEST_DATA_32B_0XAA;
	val=DMA_Channelx->CPAR;
		if(val!=TEST_DATA_32B_0XAA)
				return  (0);	
	//////////CMAR//////////////
	DMA_Channelx->CMAR=TEST_DATA_32B_0X55;
	val=DMA_Channelx->CMAR;
	if(val!=TEST_DATA_32B_0X55)
				return  (0);
	DMA_Channelx->CMAR=TEST_DATA_32B_0XAA;
	val=DMA_Channelx->CMAR;
		if(val!=TEST_DATA_32B_0XAA)
				return  (0);	
	
	DMA_Channelx->CNDTR = DMA_Channelx_tmp.CNDTR;
	DMA_Channelx->CPAR = DMA_Channelx_tmp.CPAR;
	DMA_Channelx->CMAR = DMA_Channelx_tmp.CMAR;
	DMA_Channelx->CCR = DMA_Channelx_tmp.CCR;
		
	return  (1);
}



uint8_t ADC_register_selftest(ADC_TypeDef* ADCx)
{
	unsigned long val=0;
	//unsigned int  uint_val=0;
	//////////CR1//////////////	
//	ADCx->CR1=0x00000000;
//	val=ADCx->CR1;
//	if(val!=0x00000000)
//				return  (0);
	if(ADCx==ADC1)
	{
		ADCx->CR1=0x00455555;
		val=ADCx->CR1;
		if(val!=0x00455555)
				return  (0);
		ADCx->CR1=0x008AAAAA;
		val=ADCx->CR1;
		if(val!=0x008AAAAA)
				return  (0);
	}	
	if(ADCx==ADC2)    //ADC2   16-19位是保留位
	{	
		ADCx->CR1=0x00405555;
		val=ADCx->CR1;
		if(val!=0x00405555)
				return  (0);
		ADCx->CR1=0x0080AAAA;
		val=ADCx->CR1;
		if(val!=0x0080AAAA)
					return  (0);
	}
//	//////////CR2//////////////	
//	ADCx->CR2=0x00145101;
//	val=ADCx->CR2;
//	if(val!=0x00145101)
//				return  (0);
//	ADCx->CR2=0x008AA80A;
//	val=ADCx->CR2;
//		if(val!=0x008AA80A)
//				return  (0);
	//////////SMPR1//////////////	
//	ADCx->SMPR1=0x00555555;
//	val=ADCx->SMPR1;
//	if(val!=0x00555555)
//				return  (0);
//	ADCx->SMPR1=0x00AAAAAA;
//	val=ADCx->SMPR1;
//		if(val!=0x00AAAAAA)
//				return  (0);
//	//////////SMPR2//////////////	
//	ADCx->SMPR2=0x15555555;
//	val=ADCx->SMPR2;
//	if(val!=0x15555555)
//				return  (0);
//	ADCx->SMPR2=0x2AAAAAAA;
//	val=ADCx->SMPR2;
//		if(val!=0x2AAAAAAA)
//				return  (0);				
	//////////JOFR1 //////////////	
	ADCx->JOFR1=0x00000555;
	val=ADCx->JOFR1;
	if(val!=0x00000555)
				return  (0);
	ADCx->JOFR1=0x00000AAA;
	val=ADCx->JOFR1;
		if(val!=0x00000AAA)
				return  (0);
	//////////JOFR2 //////////////	
	ADCx->JOFR2=0x00000555;
	val=ADCx->JOFR2;
	if(val!=0x00000555)
				return  (0);
	ADCx->JOFR2=0x00000AAA;
	val=ADCx->JOFR2;
		if(val!=0x00000AAA)
				return  (0);
	//////////JOFR3 //////////////	
	ADCx->JOFR3=0x00000555;
	val=ADCx->JOFR3;
	if(val!=0x00000555)
				return  (0);
	ADCx->JOFR3=0x00000AAA;
	val=ADCx->JOFR3;
		if(val!=0x00000AAA)
				return  (0);
//////////JOFR4 //////////////	
	ADCx->JOFR4=0x00000555;
	val=ADCx->JOFR4;
	if(val!=0x00000555)
				return  (0);
	ADCx->JOFR4=0x00000AAA;
	val=ADCx->JOFR4;
		if(val!=0x00000AAA)
				return  (0);		
	//////////HTR //////////////	
	ADCx->HTR=0x00000555;
	val=ADCx->HTR;
	if(val!=0x00000555)
				return  (0);
	ADCx->HTR=0x00000AAA;
	val=ADCx->HTR;
		if(val!=0x00000AAA)
				return  (0);
	//////////LTR //////////////	
	ADCx->LTR=0x00000555;
	val=ADCx->LTR;
	if(val!=0x00000555)
				return  (0);
	ADCx->LTR=0x00000AAA;
	val=ADCx->LTR;
		if(val!=0x00000AAA)
				return  (0);	
	//////////SQR1 //////////////	
	ADCx->SQR1=0x00555555;
	val=ADCx->SQR1;
	if(val!=0x00555555)
				return  (0);
	ADCx->SQR1=0x00AAAAAA;
	val=ADCx->SQR1;
		if(val!=0x00AAAAAA)
				return  (0);
		//////////SQR2//////////////	
	ADCx->SQR2=0x15555555;
	val=ADCx->SQR2;
	if(val!=0x15555555)
				return  (0);
	ADCx->SQR2=0x2AAAAAAA;
	val=ADCx->SQR2;
		if(val!=0x2AAAAAAA)
				return  (0);
	//////////SQR3//////////////	
	ADCx->SQR3=0x15555555;
	val=ADCx->SQR3;
	if(val!=0x15555555)
				return  (0);
	ADCx->SQR3=0x2AAAAAAA;
	val=ADCx->SQR3;
		if(val!=0x2AAAAAAA)
				return  (0);
	//////////JSQR//////////////	
	ADCx->JSQR=0x00155555;
	val=ADCx->JSQR;
	if(val!=0x00155555)
				return  (0);
	ADCx->JSQR=0x002AAAAA;
	val=ADCx->JSQR;
		if(val!=0x002AAAAA)
				return  (0);
	ADCx->CR1=0x00000000;
//	ADCx->CR2=0x00000000;
	ADCx->SMPR1=0x00000000;
	ADCx->SMPR2=0x00000000;
	ADCx->JOFR1=0x00000000;
	ADCx->JOFR2=0x00000000;
	ADCx->JOFR3=0x00000000;
	ADCx->JOFR4=0x00000000;
	ADCx->HTR	 =0x00000fff;
	ADCx->LTR	 =0x00000000;
	ADCx->SQR1 =0x00000000;
	ADCx->SQR2	 =0x00000000;
	ADCx->SQR3	 =0x00000000;
	ADCx->JSQR	 =0x00000000;
		
	return  (1);
}


uint8_t TIM_register_selftest(TIM_TypeDef* TIMx)
{
	uint16_t val=0;
//	unsigned int  uint_val=0;
	//////////CR1//////////////	
	TIMx->CR1=0x0105;
	val=TIMx->CR1;
	if(val!=0x0105)
				return  (0);
	TIMx->CR1=0x028A;
	val=TIMx->CR1;
	if(val!=0x028A)
				return  (0);
	TIMx->CR1=0x0000;
	//////////CR2//////////////	
	TIMx->CR2=0x5555;
	val=TIMx->CR2;
	if(val!=0x5555)
				return  (0);
	TIMx->CR2=0x2AA8;
	val=TIMx->CR2;
	if(val!=0x2AA8)
				return  (0);
	TIMx->CR2=0x0000;
	//////////SMCR//////////////	
	TIMx->SMCR=0x5555;
	val=TIMx->SMCR;
	if(val!=0x5555)
				return  (0);
	TIMx->SMCR=0xAAA2;
	val=TIMx->SMCR;
	if(val!=0xAAA2)
				return  (0);
	TIMx->SMCR=0x0000;
	//////////DIER//////////////	
	TIMx->DIER=0x5555;
	val=TIMx->DIER;
	if(val!=0x5555)
				return  (0);
	TIMx->DIER=0x2AAA;
	val=TIMx->DIER;
	if(val!=0x2AAA)
				return  (0);
	TIMx->DIER=0x0000;
	//////////CCMR1//////////////	
	TIMx->CCMR1=0x5555;
	val=TIMx->CCMR1;
	if(val!=0x5555)
				return  (0);
	TIMx->CCMR1=0xAAAA;
	val=TIMx->CCMR1;
	if(val!=0xAAAA)
				return  (0);
	TIMx->CCMR1=0x0000;
	//////////CCMR2//////////////	
	TIMx->CCMR2=0x5555;
	val=TIMx->CCMR2;
	if(val!=0x5555)
				return  (0);
	TIMx->CCMR2=0xAAAA;
	val=TIMx->CCMR2;
	if(val!=0xAAAA)
				return  (0);
	TIMx->CCMR2=0x0000;
	//////////CCER//////////////	
	TIMx->CCER=0x1555;
	val=TIMx->CCER;
	if(val!=0x1555)
				return  (0);
	TIMx->CCER=0x2AAA;
	val=TIMx->CCER;
	if(val!=0x2AAA)
				return  (0);
	TIMx->CCER=0x0000;
	//////////CNT//////////////
	TIMx->CNT=0x5555;
	val=TIMx->CNT;
	if(val!=0x5555)
				return  (0);
	TIMx->CNT=0xAAAA;
	val=TIMx->CNT;
	if(val!=0xAAAA)
				return  (0);
	TIMx->CNT=0x0000;
	//////////PSC//////////////
	TIMx->PSC=0x5555;
	val=TIMx->PSC;
	if(val!=0x5555)
				return  (0);
	TIMx->PSC=0xAAAA;
	val=TIMx->PSC;
	if(val!=0xAAAA)
				return  (0);
	TIMx->PSC=0x0000;
	//////////ARR//////////////
	TIMx->ARR=0x5555;
	val=TIMx->ARR;
	if(val!=0x5555)
				return  (0);
	TIMx->ARR=0xAAAA;
	val=TIMx->ARR;
	if(val!=0xAAAA)
				return  (0);
	TIMx->ARR=0x0000;
	//////////RCR//////////////
	TIMx->RCR=0x0055;
	val=TIMx->RCR;
	if(val!=0x0055)
				return  (0);
	TIMx->RCR=0x00AA;
	val=TIMx->RCR;
	if(val!=0x00AA)
				return  (0);
	TIMx->RCR=0x0000;
	//////////CCR1//////////////
	TIMx->CCR1=0x5555;
	val=TIMx->CCR1;
	if(val!=0x5555)
				return  (0);
	TIMx->CCR1=0xAAAA;
	val=TIMx->CCR1;
	if(val!=0xAAAA)
				return  (0);
	TIMx->CCR1=0x0000;
	//////////CCR2//////////////
	TIMx->CCR2=0x5555;
	val=TIMx->CCR2;
	if(val!=0x5555)
				return  (0);
	TIMx->CCR2=0xAAAA;
	val=TIMx->CCR2;
	if(val!=0xAAAA)
				return  (0);
	TIMx->CCR2=0x0000;
	//////////CCR3//////////////
	TIMx->CCR3=0x5555;
	val=TIMx->CCR3;
	if(val!=0x5555)
				return  (0);
	TIMx->CCR3=0xAAAA;
	val=TIMx->CCR3;
	if(val!=0xAAAA)
				return  (0);
	TIMx->CCR3=0x0000;
	//////////CCR4//////////////
	TIMx->CCR4=0x5555;
	val=TIMx->CCR4;
	if(val!=0x5555)
				return  (0);
	TIMx->CCR4=0xAAAA;
	val=TIMx->CCR4;
	if(val!=0xAAAA)
				return  (0);
	TIMx->CCR4=0x0000;
////////////BDTR//////////////
//	TIMx->BDTR=0x5455;
//	val=TIMx->BDTR;
//	if(val!=0x5455)
//				return  (12);
//	TIMx->BDTR=0xA8AA;
//	val=TIMx->BDTR;
//	if(val!=0xA8AA)
//				return  (12);
//////////DCR//////////////
	TIMx->DCR=0x1515;
	val=TIMx->DCR;
	if(val!=0x1515)
				return  (0);
	TIMx->DCR=0x0A0A;
	val=TIMx->DCR;
	if(val!=0x0A0A)
				return  (0);
	TIMx->DCR=0x0000;
	
	TIMx->SR = 0x0000;
	
	return  (1);
}