/* * Copyright (c) 2023, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * ============ ti_msp_dl_config.c ============= * Configured MSPM0 DriverLib module definitions * * DO NOT EDIT - This file is generated for the MSPM0G350X * by the SysConfig tool. */ #include "ti_msp_dl_config.h" /* * ======== SYSCFG_DL_init ======== * Perform any initialization needed before using any board APIs */ SYSCONFIG_WEAK void SYSCFG_DL_init(void) { SYSCFG_DL_initPower(); SYSCFG_DL_GPIO_init(); /* Module-Specific Initializations*/ SYSCFG_DL_SYSCTL_init(); SYSCFG_DL_UART_HMI_init(); //SYSCFG_DL_UART_BAT_init(); SYSCFG_DL_MCAN0_init(); SYSCFG_DL_SYSTICK_init(); } SYSCONFIG_WEAK void SYSCFG_DL_initPower(void) { DL_GPIO_reset(GPIOA); DL_GPIO_reset(GPIOB); DL_UART_Main_reset(UART_HMI_INST); //DL_UART_Main_reset(UART_BAT_INST); DL_MCAN_reset(MCAN0_INST); DL_GPIO_enablePower(GPIOA); DL_GPIO_enablePower(GPIOB); DL_UART_Main_enablePower(UART_HMI_INST); //DL_UART_Main_enablePower(UART_BAT_INST); DL_MCAN_enablePower(MCAN0_INST); delay_cycles(POWER_STARTUP_DELAY); } SYSCONFIG_WEAK void SYSCFG_DL_GPIO_init(void) { DL_GPIO_initPeripheralAnalogFunction(GPIO_HFXIN_IOMUX); DL_GPIO_initPeripheralAnalogFunction(GPIO_HFXOUT_IOMUX); DL_GPIO_initPeripheralOutputFunction( GPIO_UART_HMI_IOMUX_TX, GPIO_UART_HMI_IOMUX_TX_FUNC); DL_GPIO_initPeripheralInputFunction( GPIO_UART_HMI_IOMUX_RX, GPIO_UART_HMI_IOMUX_RX_FUNC); /*DL_GPIO_initPeripheralOutputFunction( GPIO_UART_BAT_IOMUX_TX, GPIO_UART_BAT_IOMUX_TX_FUNC); DL_GPIO_initPeripheralInputFunction( GPIO_UART_BAT_IOMUX_RX, GPIO_UART_BAT_IOMUX_RX_FUNC);*/ DL_GPIO_initPeripheralOutputFunction( GPIO_MCAN0_IOMUX_CAN_TX, GPIO_MCAN0_IOMUX_CAN_TX_FUNC); DL_GPIO_initPeripheralInputFunction( GPIO_MCAN0_IOMUX_CAN_RX, GPIO_MCAN0_IOMUX_CAN_RX_FUNC); DL_GPIO_initDigitalOutput(OUTPUT_POWER_EN_IOMUX); DL_GPIO_clearPins(OUTPUT_PORT, OUTPUT_POWER_EN_PIN); DL_GPIO_enableOutput(OUTPUT_PORT, OUTPUT_POWER_EN_PIN); DL_GPIO_setPins(OUTPUT_PORT, OUTPUT_POWER_EN_PIN);//电源自锁 } static const DL_SYSCTL_SYSPLLConfig gSYSPLLConfig_External = { .inputFreq = DL_SYSCTL_SYSPLL_INPUT_FREQ_8_16_MHZ, .rDivClk2x = 1, .rDivClk1 = 0, .rDivClk0 = 0, .enableCLK2x = DL_SYSCTL_SYSPLL_CLK2X_ENABLE, .enableCLK1 = DL_SYSCTL_SYSPLL_CLK1_ENABLE, .enableCLK0 = DL_SYSCTL_SYSPLL_CLK0_DISABLE, .sysPLLMCLK = DL_SYSCTL_SYSPLL_MCLK_CLK2X, .sysPLLRef = DL_SYSCTL_SYSPLL_REF_HFCLK, .qDiv = 8, .pDiv = DL_SYSCTL_SYSPLL_PDIV_1 }; static const DL_SYSCTL_SYSPLLConfig gSYSPLLConfig_Internal = { .inputFreq = DL_SYSCTL_SYSPLL_INPUT_FREQ_16_32_MHZ, .rDivClk2x = 3, .rDivClk1 = 1, .rDivClk0 = 0, .enableCLK2x = DL_SYSCTL_SYSPLL_CLK2X_ENABLE, .enableCLK1 = DL_SYSCTL_SYSPLL_CLK1_ENABLE, .enableCLK0 = DL_SYSCTL_SYSPLL_CLK0_DISABLE, .sysPLLMCLK = DL_SYSCTL_SYSPLL_MCLK_CLK2X, .sysPLLRef = DL_SYSCTL_SYSPLL_REF_SYSOSC, .qDiv = 8, .pDiv = DL_SYSCTL_SYSPLL_PDIV_2 }; void DL_SYSCTL_configSYSPLL_copy(DL_SYSCTL_SYSPLLConfig *config) { uint32_t StartUpCounter = 0; /* PLL configurations are retained in lower reset levels. Set default * behavior of disabling the PLL to keep a consistent behavior regardless * of reset level. */ DL_SYSCTL_disableSYSPLL(); /* Check that SYSPLL is disabled before configuration */ while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) != (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) { ; } // set SYSPLL reference clock DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0, ((uint32_t) config->sysPLLRef), SYSCTL_SYSPLLCFG0_SYSPLLREF_MASK); // set predivider PDIV (divides reference clock) DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, ((uint32_t) config->pDiv), SYSCTL_SYSPLLCFG1_PDIV_MASK); // save CPUSS CTL state and disable the cache uint32_t ctlTemp = DL_CORE_getInstructionConfig(); DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED, DL_CORE_LITERAL_CACHE_ENABLED); // populate SYSPLLPARAM0/1 tuning registers from flash, based on input freq SYSCTL->SOCLOCK.SYSPLLPARAM0 = *(volatile uint32_t *) ((uint32_t) config->inputFreq); SYSCTL->SOCLOCK.SYSPLLPARAM1 = *(volatile uint32_t *) ((uint32_t) config->inputFreq + (uint32_t) 0x4); // restore CPUSS CTL state CPUSS->CTL = ctlTemp; // set feedback divider QDIV (multiplies to give output frequency) DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, ((config->qDiv << SYSCTL_SYSPLLCFG1_QDIV_OFS) & SYSCTL_SYSPLLCFG1_QDIV_MASK), SYSCTL_SYSPLLCFG1_QDIV_MASK); // write clock output dividers, enable outputs, and MCLK source to SYSPLLCFG0 DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0, (((config->rDivClk2x << SYSCTL_SYSPLLCFG0_RDIVCLK2X_OFS) & SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK) | ((config->rDivClk1 << SYSCTL_SYSPLLCFG0_RDIVCLK1_OFS) & SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK) | ((config->rDivClk0 << SYSCTL_SYSPLLCFG0_RDIVCLK0_OFS) & SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK) | config->enableCLK2x | config->enableCLK1 | config->enableCLK0 | (uint32_t) config->sysPLLMCLK), (SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK | SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK | SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK | SYSCTL_SYSPLLCFG0_ENABLECLK2X_MASK | SYSCTL_SYSPLLCFG0_ENABLECLK1_MASK | SYSCTL_SYSPLLCFG0_ENABLECLK0_MASK | SYSCTL_SYSPLLCFG0_MCLK2XVCO_MASK)); // enable SYSPLL SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_SYSPLLEN_ENABLE; // wait until SYSPLL startup is stabilized while (((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK) != DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD) && (StartUpCounter < 30000)) { StartUpCounter++; } if((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK) != DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD) { DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *) &gSYSPLLConfig_Internal); } } SYSCONFIG_WEAK void SYSCFG_DL_SYSCTL_init(void) { //Low Power Mode is configured to be SLEEP0 DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0); DL_SYSCTL_setFlashWaitState(DL_SYSCTL_FLASH_WAIT_STATE_2); DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE); /* Set default configuration */ DL_SYSCTL_disableHFXT(); DL_SYSCTL_disableSYSPLL(); DL_SYSCTL_setHFCLKSourceHFXTParams(DL_SYSCTL_HFXT_RANGE_4_8_MHZ,40, false); //DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *) &gSYSPLLConfig); DL_SYSCTL_configSYSPLL_copy((DL_SYSCTL_SYSPLLConfig *) &gSYSPLLConfig_External); DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV_2); DL_SYSCTL_enableMFCLK(); DL_SYSCTL_enableMFPCLK(); DL_SYSCTL_setMFPCLKSource(DL_SYSCTL_MFPCLK_SOURCE_SYSOSC); DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK, DL_SYSCTL_HSCLK_SOURCE_SYSPLL); } static const DL_UART_Main_ClockConfig gUART_HMIClockConfig = { .clockSel = DL_UART_MAIN_CLOCK_BUSCLK, .divideRatio = DL_UART_MAIN_CLOCK_DIVIDE_RATIO_1 }; static const DL_UART_Main_Config gUART_HMIConfig = { .mode = DL_UART_MAIN_MODE_NORMAL, .direction = DL_UART_MAIN_DIRECTION_TX_RX, .flowControl = DL_UART_MAIN_FLOW_CONTROL_NONE, .parity = DL_UART_MAIN_PARITY_NONE, .wordLength = DL_UART_MAIN_WORD_LENGTH_8_BITS, .stopBits = DL_UART_MAIN_STOP_BITS_ONE }; SYSCONFIG_WEAK void SYSCFG_DL_UART_HMI_init(void) { DL_UART_Main_setClockConfig(UART_HMI_INST, (DL_UART_Main_ClockConfig *) &gUART_HMIClockConfig); DL_UART_Main_init(UART_HMI_INST, (DL_UART_Main_Config *) &gUART_HMIConfig); /* * Configure baud rate by setting oversampling and baud rate divisors. * Target baud rate: 19200 * Actual baud rate: 19200 */ DL_UART_Main_setOversampling(UART_HMI_INST, DL_UART_OVERSAMPLING_RATE_16X); DL_UART_Main_setBaudRateDivisor(UART_HMI_INST, UART_HMI_IBRD_36_MHZ_19200_BAUD, UART_HMI_FBRD_36_MHZ_19200_BAUD); /* Configure Interrupts */ DL_UART_Main_enableInterrupt(UART_HMI_INST, DL_UART_MAIN_INTERRUPT_EOT_DONE | DL_UART_MAIN_INTERRUPT_RX); /* Setting the Interrupt Priority */ NVIC_SetPriority(UART_HMI_INST_INT_IRQN, 3); DL_UART_Main_enable(UART_HMI_INST); } static const DL_UART_Main_ClockConfig gUART_BATClockConfig = { .clockSel = DL_UART_MAIN_CLOCK_BUSCLK, .divideRatio = DL_UART_MAIN_CLOCK_DIVIDE_RATIO_1 }; static const DL_UART_Main_Config gUART_BATConfig = { .mode = DL_UART_MAIN_MODE_NORMAL, .direction = DL_UART_MAIN_DIRECTION_TX_RX, .flowControl = DL_UART_MAIN_FLOW_CONTROL_NONE, .parity = DL_UART_MAIN_PARITY_NONE, .wordLength = DL_UART_MAIN_WORD_LENGTH_8_BITS, .stopBits = DL_UART_MAIN_STOP_BITS_ONE }; SYSCONFIG_WEAK void SYSCFG_DL_UART_BAT_init(void) { DL_UART_Main_setClockConfig(UART_BAT_INST, (DL_UART_Main_ClockConfig *) &gUART_BATClockConfig); DL_UART_Main_init(UART_BAT_INST, (DL_UART_Main_Config *) &gUART_BATConfig); /* * Configure baud rate by setting oversampling and baud rate divisors. * Target baud rate: 19200 * Actual baud rate: 19200 */ DL_UART_Main_setOversampling(UART_BAT_INST, DL_UART_OVERSAMPLING_RATE_16X); DL_UART_Main_setBaudRateDivisor(UART_BAT_INST, UART_BAT_IBRD_36_MHZ_19200_BAUD, UART_BAT_FBRD_36_MHZ_19200_BAUD); DL_UART_Main_enable(UART_BAT_INST); } SYSCONFIG_WEAK void SYSCFG_DL_SYSTICK_init(void) { /* * Initializes the SysTick period to 222.22 ms, * enables the interrupt, and starts the SysTick Timer */ DL_SYSTICK_config(72000); } static const DL_MCAN_ClockConfig gMCAN0ClockConf = { .clockSel = DL_MCAN_FCLK_SYSPLLCLK1, .divider = DL_MCAN_FCLK_DIV_1, }; static const DL_MCAN_InitParams gMCAN0InitParams= { /* Initialize MCAN Init parameters. */ .fdMode = false, .brsEnable = false, .txpEnable = true, .efbi = false, .pxhddisable = false, .darEnable = false, .wkupReqEnable = true, .autoWkupEnable = true, .emulationEnable = true, .tdcEnable = true, .wdcPreload = 255, /* Transmitter Delay Compensation parameters. */ .tdcConfig.tdcf = 10, .tdcConfig.tdco = 6, }; static const DL_MCAN_ConfigParams gMCAN0ConfigParams={ /* Initialize MCAN Config parameters. */ .monEnable = false, .asmEnable = false, .tsPrescalar = 15, .tsSelect = 0, .timeoutSelect = DL_MCAN_TIMEOUT_SELECT_CONT, .timeoutPreload = 65535, .timeoutCntEnable = false, .filterConfig.rrfs = true, .filterConfig.rrfe = true, .filterConfig.anfe = 0, .filterConfig.anfs = 0, }; static const DL_MCAN_MsgRAMConfigParams gMCAN0MsgRAMConfigParams ={ /* Standard ID Filter List Start Address. */ .flssa = MCAN0_INST_MCAN_STD_ID_FILT_START_ADDR, /* List Size: Standard ID. */ .lss = MCAN0_INST_MCAN_STD_ID_FILTER_NUM, /* Extended ID Filter List Start Address. */ .flesa = MCAN0_INST_MCAN_EXT_ID_FILT_START_ADDR, /* List Size: Extended ID. */ .lse = MCAN0_INST_MCAN_EXT_ID_FILTER_NUM, /* Tx Buffers Start Address. */ .txStartAddr = MCAN0_INST_MCAN_TX_BUFF_START_ADDR, /* Number of Dedicated Transmit Buffers. */ .txBufNum = MCAN0_INST_MCAN_TX_BUFF_SIZE, .txFIFOSize = 32, /* Tx Buffer Element Size. */ .txBufMode = 0, .txBufElemSize = DL_MCAN_ELEM_SIZE_8BYTES, /* Tx Event FIFO Start Address. */ .txEventFIFOStartAddr = MCAN0_INST_MCAN_TX_EVENT_START_ADDR, /* Event FIFO Size. */ .txEventFIFOSize = MCAN0_INST_MCAN_TX_EVENT_SIZE, /* Level for Tx Event FIFO watermark interrupt. */ .txEventFIFOWaterMark = 25, /* Rx FIFO0 Start Address. */ .rxFIFO0startAddr = MCAN0_INST_MCAN_FIFO_0_START_ADDR, /* Number of Rx FIFO elements. */ .rxFIFO0size = MCAN0_INST_MCAN_FIFO_0_NUM, /* Rx FIFO0 Watermark. */ .rxFIFO0waterMark = 25, .rxFIFO0OpMode = 0, /* Rx FIFO1 Start Address. */ .rxFIFO1startAddr = MCAN0_INST_MCAN_FIFO_1_START_ADDR, /* Number of Rx FIFO elements. */ .rxFIFO1size = MCAN0_INST_MCAN_FIFO_1_NUM, /* Level for Rx FIFO 1 watermark interrupt. */ .rxFIFO1waterMark = 25, /* FIFO blocking mode. */ .rxFIFO1OpMode = 0, /* Rx Buffer Start Address. */ .rxBufStartAddr = MCAN0_INST_MCAN_RX_BUFF_START_ADDR, /* Rx Buffer Element Size. */ .rxBufElemSize = DL_MCAN_ELEM_SIZE_8BYTES, /* Rx FIFO0 Element Size. */ .rxFIFO0ElemSize = DL_MCAN_ELEM_SIZE_8BYTES, /* Rx FIFO1 Element Size. */ .rxFIFO1ElemSize = DL_MCAN_ELEM_SIZE_8BYTES, }; static const DL_MCAN_BitTimingParams gMCAN0BitTimes = { /* Arbitration Baud Rate Pre-scaler. */ .nomRatePrescalar = 0, /* Arbitration Time segment before sample point. */ .nomTimeSeg1 = 124, /* Arbitration Time segment after sample point. */ .nomTimeSeg2 = 17, /* Arbitration (Re)Synchronization Jump Width Range. */ .nomSynchJumpWidth = 17, /* Data Baud Rate Pre-scaler. */ .dataRatePrescalar = 0, /* Data Time segment before sample point. */ .dataTimeSeg1 = 0, /* Data Time segment after sample point. */ .dataTimeSeg2 = 0, /* Data (Re)Synchronization Jump Width. */ .dataSynchJumpWidth = 0, }; SYSCONFIG_WEAK void SYSCFG_DL_MCAN0_init(void) { DL_MCAN_RevisionId revid_MCAN0; DL_MCAN_enableModuleClock(MCAN0_INST); DL_MCAN_setClockConfig(MCAN0_INST, (DL_MCAN_ClockConfig *) &gMCAN0ClockConf); /* Get MCANSS Revision ID. */ DL_MCAN_getRevisionId(MCAN0_INST, &revid_MCAN0); /* Wait for Memory initialization to be completed. */ while(false == DL_MCAN_isMemInitDone(MCAN0_INST)); /* Put MCAN in SW initialization mode. */ DL_MCAN_setOpMode(MCAN0_INST, DL_MCAN_OPERATION_MODE_SW_INIT); /* Wait till MCAN is not initialized. */ while (DL_MCAN_OPERATION_MODE_SW_INIT != DL_MCAN_getOpMode(MCAN0_INST)); /* Initialize MCAN module. */ DL_MCAN_init(MCAN0_INST, (DL_MCAN_InitParams *) &gMCAN0InitParams); /* Configure MCAN module. */ DL_MCAN_config(MCAN0_INST, (DL_MCAN_ConfigParams*) &gMCAN0ConfigParams); /* Configure Bit timings. */ DL_MCAN_setBitTime(MCAN0_INST, (DL_MCAN_BitTimingParams*) &gMCAN0BitTimes); /* Configure Message RAM Sections */ DL_MCAN_msgRAMConfig(MCAN0_INST, (DL_MCAN_MsgRAMConfigParams*) &gMCAN0MsgRAMConfigParams); /* Set Extended ID Mask. */ DL_MCAN_setExtIDAndMask(MCAN0_INST, MCAN0_INST_MCAN_EXT_ID_AND_MASK ); /* Loopback mode */ /* Take MCAN out of the SW initialization mode */ DL_MCAN_setOpMode(MCAN0_INST, DL_MCAN_OPERATION_MODE_NORMAL); while (DL_MCAN_OPERATION_MODE_NORMAL != DL_MCAN_getOpMode(MCAN0_INST)); /* Enable MCAN mopdule Interrupts */ DL_MCAN_enableIntr(MCAN0_INST, MCAN0_INST_MCAN_INTERRUPTS, 1U); DL_MCAN_selectIntrLine(MCAN0_INST, DL_MCAN_INTR_MASK_ALL, DL_MCAN_INTR_LINE_NUM_1); DL_MCAN_enableIntrLine(MCAN0_INST, DL_MCAN_INTR_LINE_NUM_1, 1U); /* Enable MSPM0 MCAN interrupt */ DL_MCAN_clearInterruptStatus(MCAN0_INST,(DL_MCAN_MSP_INTERRUPT_LINE1)); DL_MCAN_enableInterrupt(MCAN0_INST,(DL_MCAN_MSP_INTERRUPT_LINE1)); }