motor_bootloader/MDK-ARM/DebugConfig/Bootloader_STM32F302RBT6_STM32F302RBTx.dbgconf

// File: STM32F302.dbgconf
// Version: 1.0.0
// Note: refer to STM32F302xB/C/D/E, STM32F302x6/8 Reference manual (RM0365)
//       refer to STM32F302xB/C, STM32F302xd/E, STM32F302x6/8 datasheet

// <<< Use Configuration Wizard in Context Menu >>>

// <h> Debug MCU configuration register (DBGMCU_CR)
//   <o.2>  DBG_STANDBY              <i> Debug standby mode
//   <o.1>  DBG_STOP                 <i> Debug stop mode
//   <o.0>  DBG_SLEEP                <i> Debug sleep mode
// </h>
DbgMCU_CR = 0x00000007;

// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
//                                   <i> Reserved bits must be kept at reset value
//   <o.30> DBG_I2C3_SMBUS_TIMEOUT   <i> SMBUS timeout mode stopped when core is halted
//   <o.25> DBG_CAN_STOP             <i> Debug CAN stopped when core is halted
//   <o.22> DBG_I2C2_SMBUS_TIMEOUT   <i> SMBUS timeout mode stopped when core is halted
//   <o.21> DBG_I2C1_SMBUS_TIMEOUT   <i> SMBUS timeout mode stopped when core is halted
//   <o.12> DBG_IWDG_STOP            <i> Independent watchdog stopped when core is halted
//   <o.11> DBG_WWDG_STOP            <i> Window watchdog stopped when core is halted
//   <o.10> DBG_RTC_STOP             <i> RTC stopped when core is halted
//   <o.4>  DBG_TIM6_STOP            <i> TIM6 counter stopped when core is halted
//   <o.2>  DBG_TIM4_STOP            <i> TIM4 counter stopped when core is halted
//   <o.1>  DBG_TIM3_STOP            <i> TIM3 counter stopped when core is halted
//   <o.0>  DBG_TIM2_STOP            <i> TIM2 counter stopped when core is halted
// </h>
DbgMCU_APB1_Fz = 0x00000000;

// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
//                                   <i> Reserved bits must be kept at reset value
//   <o.4>  DBG_TIM17_STOP           <i> TIM17 counter stopped when core is halted
//   <o.3>  DBG_TIM16_STOP           <i> TIM16 counter stopped when core is halted
//   <o.2>  DBG_TIM15_STOP           <i> TIM15 counter stopped when core is halted
//   <o.0>  DBG_TIM1_STOP            <i> TIM1 counter stopped when core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;

// <h> Flash Download Options
//   <o.0> Option Byte Loading       <i> Launch the Option Byte Loading after a Flash Download by setting the OBL_LAUNCH bit (causes a reset)
// </h>
DoOptionByteLoading = 0x00000000;

// <<< end of configuration section >>>