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ti_msp_dl_config.c

@@ -179,6 +179,9 @@ SYSCONFIG_WEAK void SYSCFG_DL_GPIO_init(void)
     DL_GPIO_initPeripheralOutputFunction(GPIO_PWM_R_C1_IOMUX,GPIO_PWM_R_C1_IOMUX_FUNC);
     DL_GPIO_enableOutput(GPIO_PWM_R_C1_PORT, GPIO_PWM_R_C1_PIN);
 
+    DL_GPIO_initPeripheralAnalogFunction(GPIO_HFXIN_IOMUX);
+            DL_GPIO_initPeripheralAnalogFunction(GPIO_HFXOUT_IOMUX);
+
     DL_GPIO_initPeripheralOutputFunction(
         GPIO_UART_HMI_IOMUX_TX, GPIO_UART_HMI_IOMUX_TX_FUNC);
     DL_GPIO_initPeripheralInputFunction(
@@ -249,7 +252,20 @@ SYSCONFIG_WEAK void SYSCFG_DL_DEBUG_init(void)
     /* Set the DISABLE bit in the SWDCFG register in SYSCTL along with KEY */
     SYSCTL->SOCLOCK.SWDCFG = (SYSCTL_SWDCFG_KEY_VALUE | SYSCTL_SWDCFG_DISABLE_TRUE);
 }
-static const DL_SYSCTL_SYSPLLConfig gSYSPLLConfig = {
+static const DL_SYSCTL_SYSPLLConfig gSYSPLLConfig_External = {
+    .inputFreq              = DL_SYSCTL_SYSPLL_INPUT_FREQ_8_16_MHZ,
+    .rDivClk2x              = 1,
+    .rDivClk1               = 0,
+    .rDivClk0               = 0,
+    .enableCLK2x            = DL_SYSCTL_SYSPLL_CLK2X_ENABLE,
+    .enableCLK1             = DL_SYSCTL_SYSPLL_CLK1_ENABLE,
+    .enableCLK0             = DL_SYSCTL_SYSPLL_CLK0_DISABLE,
+    .sysPLLMCLK             = DL_SYSCTL_SYSPLL_MCLK_CLK2X,
+    .sysPLLRef              = DL_SYSCTL_SYSPLL_REF_HFCLK,
+    .qDiv                   = 8,
+    .pDiv                   = DL_SYSCTL_SYSPLL_PDIV_1
+};
+static const DL_SYSCTL_SYSPLLConfig gSYSPLLConfig_Internal = {
     .inputFreq              = DL_SYSCTL_SYSPLL_INPUT_FREQ_16_32_MHZ,
 	.rDivClk2x              = 3,
 	.rDivClk1               = 1,
@@ -262,6 +278,79 @@ static const DL_SYSCTL_SYSPLLConfig gSYSPLLConfig = {
 	.qDiv                   = 8,
 	.pDiv                   = DL_SYSCTL_SYSPLL_PDIV_2
 };
+void DL_SYSCTL_configSYSPLL_copy(DL_SYSCTL_SYSPLLConfig *config)
+{
+    uint32_t StartUpCounter = 0;
+    /* PLL configurations are retained in lower reset levels. Set default
+     * behavior of disabling the PLL to keep a consistent behavior regardless
+     * of reset level. */
+    DL_SYSCTL_disableSYSPLL();
+
+    /* Check that SYSPLL is disabled before configuration */
+    while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) !=
+           (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) {
+        ;
+    }
+
+    // set SYSPLL reference clock
+    DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0,
+        ((uint32_t) config->sysPLLRef), SYSCTL_SYSPLLCFG0_SYSPLLREF_MASK);
+
+    // set predivider PDIV (divides reference clock)
+    DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, ((uint32_t) config->pDiv),
+        SYSCTL_SYSPLLCFG1_PDIV_MASK);
+
+    // save CPUSS CTL state and disable the cache
+    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
+    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
+        DL_CORE_LITERAL_CACHE_ENABLED);
+
+    // populate SYSPLLPARAM0/1 tuning registers from flash, based on input freq
+    SYSCTL->SOCLOCK.SYSPLLPARAM0 =
+        *(volatile uint32_t *) ((uint32_t) config->inputFreq);
+    SYSCTL->SOCLOCK.SYSPLLPARAM1 =
+        *(volatile uint32_t *) ((uint32_t) config->inputFreq + (uint32_t) 0x4);
+
+    // restore CPUSS CTL state
+    CPUSS->CTL = ctlTemp;
+
+    // set feedback divider QDIV (multiplies to give output frequency)
+    DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1,
+        ((config->qDiv << SYSCTL_SYSPLLCFG1_QDIV_OFS) &
+            SYSCTL_SYSPLLCFG1_QDIV_MASK),
+        SYSCTL_SYSPLLCFG1_QDIV_MASK);
+
+    // write clock output dividers, enable outputs, and MCLK source to SYSPLLCFG0
+    DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0,
+        (((config->rDivClk2x << SYSCTL_SYSPLLCFG0_RDIVCLK2X_OFS) &
+             SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK) |
+            ((config->rDivClk1 << SYSCTL_SYSPLLCFG0_RDIVCLK1_OFS) &
+                SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK) |
+            ((config->rDivClk0 << SYSCTL_SYSPLLCFG0_RDIVCLK0_OFS) &
+                SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK) |
+            config->enableCLK2x | config->enableCLK1 | config->enableCLK0 |
+            (uint32_t) config->sysPLLMCLK),
+        (SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK | SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK |
+            SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK |
+            SYSCTL_SYSPLLCFG0_ENABLECLK2X_MASK |
+            SYSCTL_SYSPLLCFG0_ENABLECLK1_MASK |
+            SYSCTL_SYSPLLCFG0_ENABLECLK0_MASK |
+            SYSCTL_SYSPLLCFG0_MCLK2XVCO_MASK));
+
+    // enable SYSPLL
+    SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_SYSPLLEN_ENABLE;
+
+    // wait until SYSPLL startup is stabilized
+    while (((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK) != DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD) && (StartUpCounter < 30000))
+    {
+        StartUpCounter++;
+    }
+
+    if((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK) != DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD)
+    {
+        DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *) &gSYSPLLConfig_Internal);
+    }
+}
 SYSCONFIG_WEAK void SYSCFG_DL_SYSCTL_init(void)
 {
 
@@ -274,7 +363,8 @@ SYSCONFIG_WEAK void SYSCFG_DL_SYSCTL_init(void)
 	/* Set default configuration */
 	DL_SYSCTL_disableHFXT();
 	DL_SYSCTL_disableSYSPLL();
-    DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *) &gSYSPLLConfig);
+	DL_SYSCTL_setHFCLKSourceHFXTParams(DL_SYSCTL_HFXT_RANGE_4_8_MHZ,40, false);
+    DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *) &gSYSPLLConfig_External);
     DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV_2);
     DL_SYSCTL_enableMFCLK();
     DL_SYSCTL_enableMFPCLK();

ti_msp_dl_config.h

@@ -73,6 +73,11 @@ extern "C" {
 
 
 
+#define GPIO_HFXT_PORT                                                     GPIOA
+#define GPIO_HFXIN_PIN                                             DL_GPIO_PIN_5
+#define GPIO_HFXIN_IOMUX                                         (IOMUX_PINCM10)
+#define GPIO_HFXOUT_PIN                                            DL_GPIO_PIN_6
+#define GPIO_HFXOUT_IOMUX                                        (IOMUX_PINCM11)
 #define CPUCLK_FREQ                                                     72000000