/* * Copyright (c) 2023, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * ============ ti_msp_dl_config.c ============= * Configured MSPM0 DriverLib module definitions * * DO NOT EDIT - This file is generated for the MSPM0G350X * by the SysConfig tool. */ #include "ti_msp_dl_config.h" #include "syspar.h" DL_TimerA_backupConfig gMOTOR_PWMBackup; DL_TimerG_backupConfig gPWM_FBackup; DL_TimerG_backupConfig gHALLTIMERBackup; /* * ======== SYSCFG_DL_init ======== * Perform any initialization needed before using any board APIs */ SYSCONFIG_WEAK void SYSCFG_DL_init(void) { SYSCFG_DL_initPower(); SYSCFG_DL_GPIO_init(); /* Module-Specific Initializations*/ #if (SIMULATION == 0) //关闭仿真功能，SWD作前灯DCDC控制 SYSCFG_DL_DEBUG_init(); #endif SYSCFG_DL_SYSCTL_init(); SYSCFG_DL_I2C_0_init(); SYSCFG_DL_MOTOR_PWM_init(); SYSCFG_DL_PWM_F_init(); SYSCFG_DL_HALLTIMER_init(); SYSCFG_DL_HALL_CNT_init(); SYSCFG_DL_UART_HMI_init(); SYSCFG_DL_ADC12_0_init(); SYSCFG_DL_ADC12_1_init(); SYSCFG_DL_COMP_0_init(); SYSCFG_DL_OPA_BPHASE_init(); SYSCFG_DL_OPA_CPHASE_init(); SYSCFG_DL_SYSTICK_init(); SYSCFG_DL_WWDT0_init(); SYSCFG_DL_MCAN0_init(); /* Ensure backup structures have no valid state */ gMOTOR_PWMBackup.backupRdy = false; gPWM_FBackup.backupRdy = false; gHALLTIMERBackup.backupRdy = false; } /* * User should take care to save and restore register configuration in application. * See Retention Configuration section for more details. */ SYSCONFIG_WEAK bool SYSCFG_DL_saveConfiguration(void) { bool retStatus = true; retStatus &= DL_TimerA_saveConfiguration(MOTOR_PWM_INST, &gMOTOR_PWMBackup); retStatus &= DL_TimerG_saveConfiguration(PWM_F_INST, &gPWM_FBackup); retStatus &= DL_TimerG_saveConfiguration(HALLTIMER_INST, &gHALLTIMERBackup); return retStatus; } SYSCONFIG_WEAK bool SYSCFG_DL_restoreConfiguration(void) { bool retStatus = true; retStatus &= DL_TimerA_restoreConfiguration(MOTOR_PWM_INST, &gMOTOR_PWMBackup, false); retStatus &= DL_TimerG_restoreConfiguration(PWM_F_INST, &gPWM_FBackup, false); retStatus &= DL_TimerG_restoreConfiguration(HALLTIMER_INST, &gHALLTIMERBackup, false); return retStatus; } SYSCONFIG_WEAK void SYSCFG_DL_initPower(void) { DL_GPIO_reset(GPIOA); DL_GPIO_reset(GPIOB); DL_I2C_reset(I2C_0_INST); DL_TimerA_reset(MOTOR_PWM_INST); DL_TimerG_reset(PWM_F_INST); DL_TimerG_reset(HALLTIMER_INST); DL_TimerG_reset(HALL_CNT_INST); DL_UART_Main_reset(UART_HMI_INST); DL_ADC12_reset(ADC12_0_INST); DL_ADC12_reset(ADC12_1_INST); DL_COMP_reset(COMP_0_INST); DL_OPA_reset(OPA_BPHASE_INST); DL_OPA_reset(OPA_CPHASE_INST); DL_WWDT_reset(WWDT0_INST); DL_MathACL_reset(MATHACL); DL_MCAN_reset(MCAN0_INST); DL_GPIO_enablePower(GPIOA); DL_GPIO_enablePower(GPIOB); DL_I2C_enablePower(I2C_0_INST); DL_TimerA_enablePower(MOTOR_PWM_INST); DL_TimerG_enablePower(PWM_F_INST); DL_TimerG_enablePower(HALLTIMER_INST); DL_TimerG_enablePower(HALL_CNT_INST); DL_UART_Main_enablePower(UART_HMI_INST); DL_ADC12_enablePower(ADC12_0_INST); DL_ADC12_enablePower(ADC12_1_INST); DL_COMP_enablePower(COMP_0_INST); DL_OPA_enablePower(OPA_BPHASE_INST); DL_OPA_enablePower(OPA_CPHASE_INST); DL_WWDT_enablePower(WWDT0_INST); DL_MathACL_enablePower(MATHACL); DL_MCAN_enablePower(MCAN0_INST); delay_cycles(POWER_STARTUP_DELAY); } SYSCONFIG_WEAK void SYSCFG_DL_GPIO_init(void) { DL_GPIO_initPeripheralAnalogFunction(GPIO_HFXIN_IOMUX); DL_GPIO_initPeripheralAnalogFunction(GPIO_HFXOUT_IOMUX); DL_GPIO_initPeripheralInputFunctionFeatures( GPIO_I2C_0_IOMUX_SDA, GPIO_I2C_0_IOMUX_SDA_FUNC, DL_GPIO_INVERSION_DISABLE, DL_GPIO_RESISTOR_PULL_UP, DL_GPIO_HYSTERESIS_DISABLE, DL_GPIO_WAKEUP_DISABLE); DL_GPIO_initPeripheralInputFunctionFeatures( GPIO_I2C_0_IOMUX_SCL, GPIO_I2C_0_IOMUX_SCL_FUNC, DL_GPIO_INVERSION_DISABLE, DL_GPIO_RESISTOR_PULL_UP, DL_GPIO_HYSTERESIS_DISABLE, DL_GPIO_WAKEUP_DISABLE); DL_GPIO_enableHiZ(GPIO_I2C_0_IOMUX_SDA); DL_GPIO_enableHiZ(GPIO_I2C_0_IOMUX_SCL); DL_GPIO_initPeripheralOutputFunction(GPIO_MOTOR_PWM_C0_IOMUX,GPIO_MOTOR_PWM_C0_IOMUX_FUNC); DL_GPIO_enableOutput(GPIO_MOTOR_PWM_C0_PORT, GPIO_MOTOR_PWM_C0_PIN); DL_GPIO_initPeripheralOutputFunction(GPIO_MOTOR_PWM_C0_CMPL_IOMUX,GPIO_MOTOR_PWM_C0_CMPL_IOMUX_FUNC); DL_GPIO_enableOutput(GPIO_MOTOR_PWM_C0_CMPL_PORT, GPIO_MOTOR_PWM_C0_CMPL_PIN); DL_GPIO_initPeripheralOutputFunction(GPIO_MOTOR_PWM_C1_IOMUX,GPIO_MOTOR_PWM_C1_IOMUX_FUNC); DL_GPIO_enableOutput(GPIO_MOTOR_PWM_C1_PORT, GPIO_MOTOR_PWM_C1_PIN); DL_GPIO_initPeripheralOutputFunction(GPIO_MOTOR_PWM_C1_CMPL_IOMUX,GPIO_MOTOR_PWM_C1_CMPL_IOMUX_FUNC); DL_GPIO_enableOutput(GPIO_MOTOR_PWM_C1_CMPL_PORT, GPIO_MOTOR_PWM_C1_CMPL_PIN); DL_GPIO_initPeripheralOutputFunction(GPIO_MOTOR_PWM_C2_IOMUX,GPIO_MOTOR_PWM_C2_IOMUX_FUNC); DL_GPIO_enableOutput(GPIO_MOTOR_PWM_C2_PORT, GPIO_MOTOR_PWM_C2_PIN); DL_GPIO_initPeripheralOutputFunction(GPIO_MOTOR_PWM_C2_CMPL_IOMUX,GPIO_MOTOR_PWM_C2_CMPL_IOMUX_FUNC); DL_GPIO_enableOutput(GPIO_MOTOR_PWM_C2_CMPL_PORT, GPIO_MOTOR_PWM_C2_CMPL_PIN); DL_GPIO_initPeripheralOutputFunction(GPIO_PWM_F_C1_IOMUX,GPIO_PWM_F_C1_IOMUX_FUNC); DL_GPIO_enableOutput(GPIO_PWM_F_C1_PORT, GPIO_PWM_F_C1_PIN); DL_GPIO_initPeripheralOutputFunction( GPIO_UART_HMI_IOMUX_TX, GPIO_UART_HMI_IOMUX_TX_FUNC); DL_GPIO_initPeripheralInputFunction( GPIO_UART_HMI_IOMUX_RX, GPIO_UART_HMI_IOMUX_RX_FUNC); DL_GPIO_initDigitalOutput(OUTPUT_POWER_EN_IOMUX); DL_GPIO_initDigitalInput(LIGHT_DETECT_LIGHT_PWM_F_IOMUX); DL_GPIO_initDigitalInputFeatures(INPUT_BREAK_IOMUX, DL_GPIO_INVERSION_DISABLE, DL_GPIO_RESISTOR_PULL_UP, DL_GPIO_HYSTERESIS_DISABLE, DL_GPIO_WAKEUP_DISABLE); DL_GPIO_initDigitalInput(INPUT_Cadence_Dir_IOMUX); DL_GPIO_initDigitalInput(INPUT_Cadence_Speed_IOMUX); DL_GPIO_initDigitalInputFeatures(INPUT_PIN_GEAR_IOMUX, DL_GPIO_INVERSION_DISABLE, DL_GPIO_RESISTOR_PULL_UP, DL_GPIO_HYSTERESIS_DISABLE, DL_GPIO_WAKEUP_DISABLE); DL_GPIO_initDigitalInputFeatures(INPUT_Speed_In_IOMUX, DL_GPIO_INVERSION_DISABLE, DL_GPIO_RESISTOR_PULL_UP, DL_GPIO_HYSTERESIS_DISABLE, DL_GPIO_WAKEUP_DISABLE); #if 0 DL_GPIO_initDigitalInput(HALL_HALLA_IOMUX); DL_GPIO_initDigitalInput(HALL_HALLB_IOMUX); DL_GPIO_initDigitalInput(HALL_HALLC_IOMUX); #endif DL_GPIO_initDigitalOutput(GPIO_B_LED_PIN_LED_B_EN_IOMUX); DL_GPIO_initDigitalOutput(GPIO_B_LED_PIN_LED_B_SEL_IOMUX); #if (SIMULATION == 0) DL_GPIO_initDigitalOutput(GPIO_F_LED_PIN_LED_F_EN_IOMUX); DL_GPIO_initDigitalOutput(GPIO_F_LED_PIN_LED_F_SEL_IOMUX); DL_GPIO_clearPins(GPIOA, GPIO_F_LED_PIN_LED_F_EN_PIN | GPIO_F_LED_PIN_LED_F_SEL_PIN); DL_GPIO_enableOutput(GPIOA, GPIO_F_LED_PIN_LED_F_EN_PIN | GPIO_F_LED_PIN_LED_F_SEL_PIN); #endif DL_GPIO_setUpperPinsPolarity(GPIOA, DL_GPIO_PIN_23_EDGE_RISE | DL_GPIO_PIN_28_EDGE_RISE); DL_GPIO_clearInterruptStatus(GPIOA, LIGHT_DETECT_LIGHT_PWM_F_PIN); DL_GPIO_enableInterrupt(GPIOA, LIGHT_DETECT_LIGHT_PWM_F_PIN); DL_GPIO_clearPins(GPIOB, OUTPUT_POWER_EN_PIN | GPIO_B_LED_PIN_LED_B_EN_PIN | GPIO_B_LED_PIN_LED_B_SEL_PIN); DL_GPIO_enableOutput(GPIOB, OUTPUT_POWER_EN_PIN | GPIO_B_LED_PIN_LED_B_EN_PIN | GPIO_B_LED_PIN_LED_B_SEL_PIN); DL_GPIO_initPeripheralOutputFunction( GPIO_MCAN0_IOMUX_CAN_TX, GPIO_MCAN0_IOMUX_CAN_TX_FUNC); DL_GPIO_initPeripheralInputFunction( GPIO_MCAN0_IOMUX_CAN_RX, GPIO_MCAN0_IOMUX_CAN_RX_FUNC); } SYSCONFIG_WEAK void SYSCFG_DL_DEBUG_init(void) { /* Set the DISABLE bit in the SWDCFG register in SYSCTL along with KEY */ SYSCTL->SOCLOCK.SWDCFG = (SYSCTL_SWDCFG_KEY_VALUE | SYSCTL_SWDCFG_DISABLE_TRUE); } static const DL_SYSCTL_SYSPLLConfig gSYSPLLConfig = { .inputFreq = DL_SYSCTL_SYSPLL_INPUT_FREQ_8_16_MHZ, .rDivClk2x = 3, .rDivClk1 = 1, .rDivClk0 = 0, .enableCLK2x = DL_SYSCTL_SYSPLL_CLK2X_ENABLE, .enableCLK1 = DL_SYSCTL_SYSPLL_CLK1_ENABLE, .enableCLK0 = DL_SYSCTL_SYSPLL_CLK0_DISABLE, .sysPLLMCLK = DL_SYSCTL_SYSPLL_MCLK_CLK2X, .sysPLLRef = DL_SYSCTL_SYSPLL_REF_HFCLK, .qDiv = 17, .pDiv = DL_SYSCTL_SYSPLL_PDIV_1 }; SYSCONFIG_WEAK void SYSCFG_DL_SYSCTL_init(void) { //Low Power Mode is configured to be SLEEP0 DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0); DL_SYSCTL_setFlashWaitState(DL_SYSCTL_FLASH_WAIT_STATE_2); DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE); /* Set default configuration */ DL_SYSCTL_disableHFXT(); DL_SYSCTL_disableSYSPLL(); DL_SYSCTL_setHFCLKSourceHFXTParams(DL_SYSCTL_HFXT_RANGE_4_8_MHZ,200, false); DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *) &gSYSPLLConfig); DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV_2); DL_SYSCTL_enableMFCLK(); DL_SYSCTL_enableMFPCLK(); DL_SYSCTL_setMFPCLKSource(DL_SYSCTL_MFPCLK_SOURCE_SYSOSC); DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK, DL_SYSCTL_HSCLK_SOURCE_SYSPLL); /* INT_GROUP1 Priority */ NVIC_SetPriority(GPIOA_INT_IRQn, 1); } static const DL_I2C_ClockConfig gI2C_0ClockConfig = { .clockSel = DL_I2C_CLOCK_BUSCLK, .divideRatio = DL_I2C_CLOCK_DIVIDE_1, }; SYSCONFIG_WEAK void SYSCFG_DL_I2C_0_init(void) { DL_I2C_setClockConfig(I2C_0_INST, (DL_I2C_ClockConfig *) &gI2C_0ClockConfig); // DL_I2C_setAnalogGlitchFilterPulseWidth(I2C_0_INST, // DL_I2C_ANALOG_GLITCH_FILTER_WIDTH_50NS); DL_I2C_disableAnalogGlitchFilter(I2C_0_INST); /* Configure Controller Mode */ DL_I2C_resetControllerTransfer(I2C_0_INST); /* Set frequency to 800000 Hz*/ DL_I2C_setTimerPeriod(I2C_0_INST, 3); DL_I2C_setControllerTXFIFOThreshold(I2C_0_INST, DL_I2C_TX_FIFO_LEVEL_BYTES_1); DL_I2C_setControllerRXFIFOThreshold(I2C_0_INST, DL_I2C_RX_FIFO_LEVEL_BYTES_1); DL_I2C_enableControllerClockStretching(I2C_0_INST); /* Configure Interrupts */ // DL_I2C_enableInterrupt(I2C_0_INST, // DL_I2C_INTERRUPT_CONTROLLER_ARBITRATION_LOST | // DL_I2C_INTERRUPT_CONTROLLER_NACK | // DL_I2C_INTERRUPT_CONTROLLER_RXFIFO_TRIGGER | // DL_I2C_INTERRUPT_CONTROLLER_RX_DONE | // DL_I2C_INTERRUPT_CONTROLLER_TX_DONE); // NVIC_SetPriority(I2C_0_INST_INT_IRQN, 0); /* Enable module */ DL_I2C_enableController(I2C_0_INST); } /* * Timer clock configuration to be sourced by / 1 (72000000 Hz) * timerClkFreq = (timerClkSrc / (timerClkDivRatio * (timerClkPrescale + 1))) * 72000000 Hz = 72000000 Hz / (1 * (0 + 1)) */ static const DL_TimerA_ClockConfig gMOTOR_PWMClockConfig = { .clockSel = DL_TIMER_CLOCK_BUSCLK, .divideRatio = DL_TIMER_CLOCK_DIVIDE_1, .prescale = 0U }; static const DL_TimerA_PWMConfig gMOTOR_PWMConfig = { .pwmMode = DL_TIMER_PWM_MODE_CENTER_ALIGN, .period = 4500, .isTimerWithFourCC = true, .startTimer = DL_TIMER_STOP, }; SYSCONFIG_WEAK void SYSCFG_DL_MOTOR_PWM_init(void) { DL_TimerA_setClockConfig( MOTOR_PWM_INST, (DL_TimerA_ClockConfig *) &gMOTOR_PWMClockConfig); DL_TimerA_initPWMMode( MOTOR_PWM_INST, (DL_TimerA_PWMConfig *) &gMOTOR_PWMConfig); DL_TimerA_setCaptureCompareOutCtl(MOTOR_PWM_INST, DL_TIMER_CC_OCTL_INIT_VAL_LOW, DL_TIMER_CC_OCTL_INV_OUT_DISABLED, DL_TIMER_CC_OCTL_SRC_DEAD_BAND, DL_TIMERA_CAPTURE_COMPARE_0_INDEX); DL_TimerA_setCaptCompUpdateMethod(MOTOR_PWM_INST, DL_TIMER_CC_UPDATE_METHOD_IMMEDIATE, DL_TIMERA_CAPTURE_COMPARE_0_INDEX); DL_TimerA_setCaptureCompareValue(MOTOR_PWM_INST, 1688, DL_TIMER_CC_0_INDEX); DL_TimerA_setCaptureCompareOutCtl(MOTOR_PWM_INST, DL_TIMER_CC_OCTL_INIT_VAL_LOW, DL_TIMER_CC_OCTL_INV_OUT_DISABLED, DL_TIMER_CC_OCTL_SRC_DEAD_BAND, DL_TIMERA_CAPTURE_COMPARE_1_INDEX); DL_TimerA_setCaptCompUpdateMethod(MOTOR_PWM_INST, DL_TIMER_CC_UPDATE_METHOD_IMMEDIATE, DL_TIMERA_CAPTURE_COMPARE_1_INDEX); DL_TimerA_setCaptureCompareValue(MOTOR_PWM_INST, 2250, DL_TIMER_CC_1_INDEX); DL_TimerA_setCaptureCompareOutCtl(MOTOR_PWM_INST, DL_TIMER_CC_OCTL_INIT_VAL_LOW, DL_TIMER_CC_OCTL_INV_OUT_DISABLED, DL_TIMER_CC_OCTL_SRC_DEAD_BAND, DL_TIMERA_CAPTURE_COMPARE_2_INDEX); DL_TimerA_setCaptCompUpdateMethod(MOTOR_PWM_INST, DL_TIMER_CC_UPDATE_METHOD_IMMEDIATE, DL_TIMERA_CAPTURE_COMPARE_2_INDEX); DL_TimerA_setCaptureCompareValue(MOTOR_PWM_INST, 1125, DL_TIMER_CC_2_INDEX); DL_TimerA_setDeadBand(MOTOR_PWM_INST, 108, 72, DL_TIMER_DEAD_BAND_MODE_1); DL_TimerA_setRepeatCounter(MOTOR_PWM_INST, MOTOR_PWM_REPEAT_COUNT_2); DL_TimerA_enableClock(MOTOR_PWM_INST); DL_TimerA_enableEvent(MOTOR_PWM_INST, DL_TIMERA_EVENT_ROUTE_1, (DL_TIMERA_EVENT_CC4_DN_EVENT | DL_TIMERA_EVENT_CC4_UP_EVENT)); DL_TimerA_setPublisherChanID(MOTOR_PWM_INST, DL_TIMERA_PUBLISHER_INDEX_0, MOTOR_PWM_INST_PUB_0_CH); DL_TimerA_enableInterrupt(MOTOR_PWM_INST , DL_TIMERA_INTERRUPT_FAULT_EVENT | DL_TIMER_INTERRUPT_LOAD_EVENT | DL_TIMER_INTERRUPT_ZERO_EVENT); NVIC_SetPriority(MOTOR_PWM_INST_INT_IRQN, 0); DL_TimerA_setCCPDirection(MOTOR_PWM_INST , DL_TIMER_CC0_OUTPUT | DL_TIMER_CC1_OUTPUT | DL_TIMER_CC2_OUTPUT ); DL_TimerA_setCaptureCompareInput(MOTOR_PWM_INST, DL_TIMER_CC_INPUT_INV_NOINVERT, DL_TIMER_CC_IN_SEL_TRIG, DL_TIMER_CC_0_INDEX); DL_TimerA_setCaptureCompareInput(MOTOR_PWM_INST, DL_TIMER_CC_INPUT_INV_NOINVERT, DL_TIMER_CC_IN_SEL_TRIG, DL_TIMER_CC_1_INDEX); DL_TimerA_setCaptureCompareInput(MOTOR_PWM_INST, DL_TIMER_CC_INPUT_INV_NOINVERT, DL_TIMER_CC_IN_SEL_TRIG, DL_TIMER_CC_2_INDEX); /* * Determines the external triggering event to trigger the module (self-triggered in main configuration) * and triggered by specific timer in secondary configuration */ DL_TimerA_setExternalTriggerEvent(MOTOR_PWM_INST,DL_TIMER_EXT_TRIG_SEL_TRIG_1); DL_TimerA_enableExternalTrigger(MOTOR_PWM_INST); uint32_t temp; temp = DL_TimerA_getCaptureCompareCtl(MOTOR_PWM_INST, DL_TIMER_CC_0_INDEX); DL_TimerA_setCaptureCompareCtl(MOTOR_PWM_INST, DL_TIMER_CC_MODE_COMPARE, temp | (uint32_t) DL_TIMER_CC_LCOND_TRIG_RISE, DL_TIMER_CC_0_INDEX); temp = DL_TimerA_getCaptureCompareCtl(MOTOR_PWM_INST, DL_TIMER_CC_1_INDEX); DL_TimerA_setCaptureCompareCtl(MOTOR_PWM_INST, DL_TIMER_CC_MODE_COMPARE, temp | (uint32_t) DL_TIMER_CC_LCOND_TRIG_RISE, DL_TIMER_CC_1_INDEX); temp = DL_TimerA_getCaptureCompareCtl(MOTOR_PWM_INST, DL_TIMER_CC_2_INDEX); DL_TimerA_setCaptureCompareCtl(MOTOR_PWM_INST, DL_TIMER_CC_MODE_COMPARE, temp | (uint32_t) DL_TIMER_CC_LCOND_TRIG_RISE, DL_TIMER_CC_2_INDEX); DL_TimerA_setFaultSourceConfig(MOTOR_PWM_INST, (DL_TIMERA_FAULT_SOURCE_COMP1_SENSE_LOW)); DL_TimerA_setFaultConfig(MOTOR_PWM_INST, DL_TIMERA_FAULT_CONFIG_TFIM_DISABLED | DL_TIMERA_FAULT_CONFIG_FL_LATCH_LD_CLR | DL_TIMERA_FAULT_CONFIG_FI_INDEPENDENT | DL_TIMERA_FAULT_CONFIG_FIEN_DISABLED); DL_TimerA_setFaultInputFilterConfig(MOTOR_PWM_INST, DL_TIMERA_FAULT_FILTER_FILTERED, DL_TIMERA_FAULT_FILTER_CPV_CONSEC_PER, DL_TIMERA_FAULT_FILTER_FP_PER_8); DL_TimerA_configFaultOutputAction(MOTOR_PWM_INST, DL_TIMERA_FAULT_ENTRY_CCP_LOW, DL_TIMERA_FAULT_EXIT_CCP_LOW, DL_TIMER_CC_0_INDEX); DL_TimerA_configFaultOutputAction(MOTOR_PWM_INST, DL_TIMERA_FAULT_ENTRY_CCP_LOW, DL_TIMERA_FAULT_EXIT_CCP_LOW, DL_TIMER_CC_1_INDEX); DL_TimerA_configFaultOutputAction(MOTOR_PWM_INST, DL_TIMERA_FAULT_ENTRY_CCP_LOW, DL_TIMERA_FAULT_EXIT_CCP_LOW, DL_TIMER_CC_2_INDEX); DL_TimerA_configFaultCounter(MOTOR_PWM_INST, DL_TIMERA_FAULT_ENTRY_CTR_CONT_COUNT, DL_TIMERA_FAULT_EXIT_CTR_CVAE_ACTION); DL_TimerA_enableFaultInput(MOTOR_PWM_INST); DL_TimerA_enableClockFaultDetection(MOTOR_PWM_INST); } /* * Timer clock configuration to be sourced by / 2 (36000000 Hz) * timerClkFreq = (timerClkSrc / (timerClkDivRatio * (timerClkPrescale + 1))) * 36000000 Hz = 36000000 Hz / (2 * (0 + 1)) */ static const DL_TimerG_ClockConfig gPWM_FClockConfig = { .clockSel = DL_TIMER_CLOCK_BUSCLK, .divideRatio = DL_TIMER_CLOCK_DIVIDE_2, .prescale = 0U }; static const DL_TimerG_PWMConfig gPWM_FConfig = { .pwmMode = DL_TIMER_PWM_MODE_EDGE_ALIGN_UP, .period = 2304, .startTimer = DL_TIMER_STOP, }; SYSCONFIG_WEAK void SYSCFG_DL_PWM_F_init(void) { DL_TimerG_setClockConfig( PWM_F_INST, (DL_TimerG_ClockConfig *) &gPWM_FClockConfig); DL_TimerG_initPWMMode( PWM_F_INST, (DL_TimerG_PWMConfig *) &gPWM_FConfig); DL_TimerG_setCaptureCompareOutCtl(PWM_F_INST, DL_TIMER_CC_OCTL_INIT_VAL_LOW, DL_TIMER_CC_OCTL_INV_OUT_DISABLED, DL_TIMER_CC_OCTL_SRC_FUNCVAL, DL_TIMERG_CAPTURE_COMPARE_1_INDEX); DL_TimerG_setCaptCompUpdateMethod(PWM_F_INST, DL_TIMER_CC_UPDATE_METHOD_IMMEDIATE, DL_TIMERG_CAPTURE_COMPARE_1_INDEX); DL_TimerG_setCaptureCompareValue(PWM_F_INST, 0, DL_TIMER_CC_1_INDEX); DL_TimerG_enableClock(PWM_F_INST); DL_TimerG_setCCPDirection(PWM_F_INST , DL_TIMER_CC1_OUTPUT ); } /* * Timer clock configuration to be sourced by BUSCLK / (14400000 Hz) * timerClkFreq = (timerClkSrc / (timerClkDivRatio * (timerClkPrescale + 1))) * 3600000 Hz = 14400000 Hz / (5 * (3 + 1)) */ static const DL_TimerG_ClockConfig gHALLTIMERClockConfig = { .clockSel = DL_TIMER_CLOCK_BUSCLK, .divideRatio = DL_TIMER_CLOCK_DIVIDE_5, .prescale = 3U, }; /* * Timer load value (where the counter starts from) is calculated as (timerPeriod * timerClockFreq) - 1 * HALLTIMER_INST_LOAD_VALUE = (16.67 ms * 3600000 Hz) - 1 */ static const DL_TimerG_TimerConfig gHALLTIMERTimerConfig = { .period = HALLTIMER_INST_LOAD_VALUE, .timerMode = DL_TIMER_TIMER_MODE_PERIODIC_UP, .startTimer = DL_TIMER_START, }; SYSCONFIG_WEAK void SYSCFG_DL_HALLTIMER_init(void) { DL_TimerG_setClockConfig(HALLTIMER_INST, (DL_TimerG_ClockConfig *) &gHALLTIMERClockConfig); DL_TimerG_initTimerMode(HALLTIMER_INST, (DL_TimerG_TimerConfig *) &gHALLTIMERTimerConfig); DL_TimerG_enableInterrupt(HALLTIMER_INST , DL_TIMERG_INTERRUPT_LOAD_EVENT); NVIC_SetPriority(HALLTIMER_INST_INT_IRQN, 1); DL_TimerG_enableClock(HALLTIMER_INST); } /* * Timer clock configuration to be sourced by BUSCLK / (36000000 Hz) * timerClkFreq = (timerClkSrc / (timerClkDivRatio * (timerClkPrescale + 1))) * 36000000 Hz = 36000000 Hz / (1 * (0 + 1)) */ static const DL_TimerG_ClockConfig gHALL_CNTClockConfig = { .clockSel = DL_TIMER_CLOCK_BUSCLK, .divideRatio = DL_TIMER_CLOCK_DIVIDE_1, .prescale = 0U, }; /* * Timer load value (where the counter starts from) is calculated as (timerPeriod * timerClockFreq) - 1 * HALL_CNT_INST_LOAD_VALUE = (0.03ms * 36000000 Hz) - 1 */ static const DL_TimerG_TimerConfig gHALL_CNTTimerConfig = { .period = HALL_CNT_INST_LOAD_VALUE, .timerMode = DL_TIMER_TIMER_MODE_PERIODIC_UP, .startTimer = DL_TIMER_START, }; SYSCONFIG_WEAK void SYSCFG_DL_HALL_CNT_init(void) { DL_TimerG_setClockConfig(HALL_CNT_INST, (DL_TimerG_ClockConfig *) &gHALL_CNTClockConfig); DL_TimerG_initTimerMode(HALL_CNT_INST, (DL_TimerG_TimerConfig *) &gHALL_CNTTimerConfig); DL_TimerG_enableInterrupt(HALL_CNT_INST , DL_TIMERG_INTERRUPT_ZERO_EVENT); NVIC_SetPriority(HALL_CNT_INST_INT_IRQN, 3); DL_TimerG_enableClock(HALL_CNT_INST); } static const DL_UART_Main_ClockConfig gUART_HMIClockConfig = { .clockSel = DL_UART_MAIN_CLOCK_BUSCLK, .divideRatio = DL_UART_MAIN_CLOCK_DIVIDE_RATIO_1 }; static const DL_UART_Main_Config gUART_HMIConfig = { .mode = DL_UART_MAIN_MODE_NORMAL, .direction = DL_UART_MAIN_DIRECTION_TX_RX, .flowControl = DL_UART_MAIN_FLOW_CONTROL_NONE, .parity = DL_UART_MAIN_PARITY_NONE, .wordLength = DL_UART_MAIN_WORD_LENGTH_8_BITS, .stopBits = DL_UART_MAIN_STOP_BITS_ONE }; SYSCONFIG_WEAK void SYSCFG_DL_UART_HMI_init(void) { DL_UART_Main_setClockConfig(UART_HMI_INST, (DL_UART_Main_ClockConfig *) &gUART_HMIClockConfig); DL_UART_Main_init(UART_HMI_INST, (DL_UART_Main_Config *) &gUART_HMIConfig); /* * Configure baud rate by setting oversampling and baud rate divisors. * Target baud rate: 9600 * Actual baud rate: 9600 */ DL_UART_Main_setOversampling(UART_HMI_INST, DL_UART_OVERSAMPLING_RATE_16X); DL_UART_Main_setBaudRateDivisor(UART_HMI_INST, UART_HMI_IBRD_36_MHZ_9600_BAUD, UART_HMI_FBRD_36_MHZ_9600_BAUD); /* Configure Interrupts */ DL_UART_Main_enableInterrupt(UART_HMI_INST, DL_UART_MAIN_INTERRUPT_EOT_DONE | DL_UART_MAIN_INTERRUPT_RX); /* Setting the Interrupt Priority */ NVIC_SetPriority(UART_HMI_INST_INT_IRQN, 3); DL_UART_Main_enable(UART_HMI_INST); } /* ADC12_0 Initialization */ static const DL_ADC12_ClockConfig gADC12_0ClockConfig = { .clockSel = DL_ADC12_CLOCK_SYSOSC, .divideRatio = DL_ADC12_CLOCK_DIVIDE_1, .freqRange = DL_ADC12_CLOCK_FREQ_RANGE_24_TO_32, }; SYSCONFIG_WEAK void SYSCFG_DL_ADC12_0_init(void) { DL_ADC12_setClockConfig(ADC12_0_INST, (DL_ADC12_ClockConfig *) &gADC12_0ClockConfig); DL_ADC12_initSeqSample(ADC12_0_INST, DL_ADC12_REPEAT_MODE_ENABLED, DL_ADC12_SAMPLING_SOURCE_AUTO, DL_ADC12_TRIG_SRC_EVENT, DL_ADC12_SEQ_START_ADDR_00, DL_ADC12_SEQ_END_ADDR_04, DL_ADC12_SAMP_CONV_RES_12_BIT, DL_ADC12_SAMP_CONV_DATA_FORMAT_UNSIGNED); DL_ADC12_configConversionMem(ADC12_0_INST, ADC12_0_ADCMEM_0, DL_ADC12_INPUT_CHAN_13, DL_ADC12_REFERENCE_VOLTAGE_VDDA, DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP1, DL_ADC12_AVERAGING_MODE_DISABLED, DL_ADC12_BURN_OUT_SOURCE_DISABLED, DL_ADC12_TRIGGER_MODE_AUTO_NEXT, DL_ADC12_WINDOWS_COMP_MODE_DISABLED); DL_ADC12_configConversionMem(ADC12_0_INST, ADC12_0_ADCMEM_1, DL_ADC12_INPUT_CHAN_6, DL_ADC12_REFERENCE_VOLTAGE_VDDA, DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP0, DL_ADC12_AVERAGING_MODE_DISABLED, DL_ADC12_BURN_OUT_SOURCE_DISABLED, DL_ADC12_TRIGGER_MODE_AUTO_NEXT, DL_ADC12_WINDOWS_COMP_MODE_DISABLED); DL_ADC12_configConversionMem(ADC12_0_INST, ADC12_0_ADCMEM_2, DL_ADC12_INPUT_CHAN_12, DL_ADC12_REFERENCE_VOLTAGE_VDDA, DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP0, DL_ADC12_AVERAGING_MODE_DISABLED, DL_ADC12_BURN_OUT_SOURCE_DISABLED, DL_ADC12_TRIGGER_MODE_AUTO_NEXT, DL_ADC12_WINDOWS_COMP_MODE_DISABLED); DL_ADC12_configConversionMem(ADC12_0_INST, ADC12_0_ADCMEM_3, DL_ADC12_INPUT_CHAN_0, DL_ADC12_REFERENCE_VOLTAGE_VDDA, DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP0, DL_ADC12_AVERAGING_MODE_DISABLED, DL_ADC12_BURN_OUT_SOURCE_DISABLED, DL_ADC12_TRIGGER_MODE_AUTO_NEXT, DL_ADC12_WINDOWS_COMP_MODE_DISABLED); DL_ADC12_configConversionMem(ADC12_0_INST, ADC12_0_ADCMEM_4, DL_ADC12_INPUT_CHAN_1, DL_ADC12_REFERENCE_VOLTAGE_VDDA, DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP0, DL_ADC12_AVERAGING_MODE_DISABLED, DL_ADC12_BURN_OUT_SOURCE_DISABLED, DL_ADC12_TRIGGER_MODE_TRIGGER_NEXT, DL_ADC12_WINDOWS_COMP_MODE_DISABLED); DL_ADC12_setPowerDownMode(ADC12_0_INST,DL_ADC12_POWER_DOWN_MODE_MANUAL); DL_ADC12_setSampleTime0(ADC12_0_INST,32); DL_ADC12_setSampleTime1(ADC12_0_INST,32); DL_ADC12_setSubscriberChanID(ADC12_0_INST,ADC12_0_INST_SUB_CH); /* Enable ADC12 interrupt */ DL_ADC12_clearInterruptStatus(ADC12_0_INST,(DL_ADC12_INTERRUPT_MEM1_RESULT_LOADED)); DL_ADC12_enableInterrupt(ADC12_0_INST,(DL_ADC12_INTERRUPT_MEM1_RESULT_LOADED)); NVIC_SetPriority(ADC12_0_INST_INT_IRQN, 2); DL_ADC12_enableConversions(ADC12_0_INST); } /* ADC12_1 Initialization */ static const DL_ADC12_ClockConfig gADC12_1ClockConfig = { .clockSel = DL_ADC12_CLOCK_SYSOSC, .divideRatio = DL_ADC12_CLOCK_DIVIDE_1, .freqRange = DL_ADC12_CLOCK_FREQ_RANGE_24_TO_32, }; SYSCONFIG_WEAK void SYSCFG_DL_ADC12_1_init(void) { DL_ADC12_setClockConfig(ADC12_1_INST, (DL_ADC12_ClockConfig *) &gADC12_1ClockConfig); DL_ADC12_initSeqSample(ADC12_1_INST, DL_ADC12_REPEAT_MODE_ENABLED, DL_ADC12_SAMPLING_SOURCE_AUTO, DL_ADC12_TRIG_SRC_EVENT, DL_ADC12_SEQ_START_ADDR_00, DL_ADC12_SEQ_END_ADDR_05, DL_ADC12_SAMP_CONV_RES_12_BIT, DL_ADC12_SAMP_CONV_DATA_FORMAT_UNSIGNED); DL_ADC12_configConversionMem(ADC12_1_INST, ADC12_1_ADCMEM_0, DL_ADC12_INPUT_CHAN_13, DL_ADC12_REFERENCE_VOLTAGE_VDDA, DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP1, DL_ADC12_AVERAGING_MODE_DISABLED, DL_ADC12_BURN_OUT_SOURCE_DISABLED, DL_ADC12_TRIGGER_MODE_AUTO_NEXT, DL_ADC12_WINDOWS_COMP_MODE_DISABLED); DL_ADC12_configConversionMem(ADC12_1_INST, ADC12_1_ADCMEM_1, DL_ADC12_INPUT_CHAN_6, DL_ADC12_REFERENCE_VOLTAGE_VDDA, DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP0, DL_ADC12_AVERAGING_MODE_DISABLED, DL_ADC12_BURN_OUT_SOURCE_DISABLED, DL_ADC12_TRIGGER_MODE_AUTO_NEXT, DL_ADC12_WINDOWS_COMP_MODE_DISABLED); DL_ADC12_configConversionMem(ADC12_1_INST, ADC12_1_ADCMEM_2, DL_ADC12_INPUT_CHAN_5, DL_ADC12_REFERENCE_VOLTAGE_VDDA, DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP0, DL_ADC12_AVERAGING_MODE_DISABLED, DL_ADC12_BURN_OUT_SOURCE_DISABLED, DL_ADC12_TRIGGER_MODE_AUTO_NEXT, DL_ADC12_WINDOWS_COMP_MODE_DISABLED); DL_ADC12_configConversionMem(ADC12_1_INST, ADC12_1_ADCMEM_3, DL_ADC12_INPUT_CHAN_4, DL_ADC12_REFERENCE_VOLTAGE_VDDA, DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP0, DL_ADC12_AVERAGING_MODE_DISABLED, DL_ADC12_BURN_OUT_SOURCE_DISABLED, DL_ADC12_TRIGGER_MODE_AUTO_NEXT, DL_ADC12_WINDOWS_COMP_MODE_DISABLED); DL_ADC12_configConversionMem(ADC12_1_INST, ADC12_1_ADCMEM_4, DL_ADC12_INPUT_CHAN_7, DL_ADC12_REFERENCE_VOLTAGE_VDDA, DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP0, DL_ADC12_AVERAGING_MODE_DISABLED, DL_ADC12_BURN_OUT_SOURCE_DISABLED, DL_ADC12_TRIGGER_MODE_AUTO_NEXT, DL_ADC12_WINDOWS_COMP_MODE_DISABLED); DL_ADC12_configConversionMem(ADC12_1_INST, ADC12_1_ADCMEM_5, DL_ADC12_INPUT_CHAN_0, DL_ADC12_REFERENCE_VOLTAGE_VDDA, DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP0, DL_ADC12_AVERAGING_MODE_DISABLED, DL_ADC12_BURN_OUT_SOURCE_DISABLED, DL_ADC12_TRIGGER_MODE_TRIGGER_NEXT, DL_ADC12_WINDOWS_COMP_MODE_DISABLED); DL_ADC12_setSampleTime0(ADC12_1_INST,32); DL_ADC12_setSampleTime1(ADC12_1_INST,32); DL_ADC12_setSubscriberChanID(ADC12_1_INST,ADC12_1_INST_SUB_CH); DL_ADC12_enableConversions(ADC12_1_INST); } /* COMP_0 Initialization */ static const DL_COMP_Config gCOMP_0Config = { .channelEnable = DL_COMP_ENABLE_CHANNEL_POS, .mode = DL_COMP_MODE_FAST, .negChannel = DL_COMP_IMSEL_CHANNEL_1, .posChannel = DL_COMP_IPSEL_CHANNEL_1, .hysteresis = DL_COMP_HYSTERESIS_NONE, .polarity = DL_COMP_POLARITY_INV }; static const DL_COMP_RefVoltageConfig gCOMP_0VRefConfig = { .mode = DL_COMP_REF_MODE_STATIC, .source = DL_COMP_REF_SOURCE_VDDA_DAC, .terminalSelect = DL_COMP_REF_TERMINAL_SELECT_NEG, .controlSelect = DL_COMP_DAC_CONTROL_SW, .inputSelect = DL_COMP_DAC_INPUT_DACCODE0 }; SYSCONFIG_WEAK void SYSCFG_DL_COMP_0_init(void) { DL_COMP_init(COMP_0_INST, (DL_COMP_Config *) &gCOMP_0Config); DL_COMP_refVoltageInit(COMP_0_INST, (DL_COMP_RefVoltageConfig *) &gCOMP_0VRefConfig); DL_COMP_setDACCode0(COMP_0_INST, COMP_0_DACCODE0); DL_COMP_enable(COMP_0_INST); } static const DL_OPA_Config gOPA_BPHASEConfig0 = { .pselChannel = DL_OPA_PSEL_IN1_POS, .nselChannel = DL_OPA_NSEL_IN1_NEG, .mselChannel = DL_OPA_MSEL_OPEN, .gain = DL_OPA_GAIN_N0_P1, .outputPinState = DL_OPA_OUTPUT_PIN_ENABLED, .choppingMode = DL_OPA_CHOPPING_MODE_DISABLE, }; SYSCONFIG_WEAK void SYSCFG_DL_OPA_BPHASE_init(void) { DL_OPA_init(OPA_BPHASE_INST, (DL_OPA_Config *) &gOPA_BPHASEConfig0); DL_OPA_setGainBandwidth(OPA_BPHASE_INST, DL_OPA_GBW_HIGH); DL_OPA_enable(OPA_BPHASE_INST); } static const DL_OPA_Config gOPA_CPHASEConfig0 = { .pselChannel = DL_OPA_PSEL_IN1_POS, .nselChannel = DL_OPA_NSEL_IN1_NEG, .mselChannel = DL_OPA_MSEL_OPEN, .gain = DL_OPA_GAIN_N0_P1, .outputPinState = DL_OPA_OUTPUT_PIN_ENABLED, .choppingMode = DL_OPA_CHOPPING_MODE_DISABLE, }; SYSCONFIG_WEAK void SYSCFG_DL_OPA_CPHASE_init(void) { DL_OPA_init(OPA_CPHASE_INST, (DL_OPA_Config *) &gOPA_CPHASEConfig0); DL_OPA_setGainBandwidth(OPA_CPHASE_INST, DL_OPA_GBW_HIGH); DL_OPA_enable(OPA_CPHASE_INST); } SYSCONFIG_WEAK void SYSCFG_DL_SYSTICK_init(void) { /* * Initializes the SysTick period to 1.00 ms, * enables the interrupt, and starts the SysTick Timer */ DL_SYSTICK_config(72000); } SYSCONFIG_WEAK void SYSCFG_DL_WWDT0_init(void) { /* * Initialize WWDT0 in Watchdog mode with following settings * Watchdog Source Clock = (LFCLK Freq) / (WWDT Clock Divider) * = 32768Hz / 4 = 8.19 kHz * Watchdog Period = (WWDT Clock Divider) ∗ (WWDT Period Count) / 32768Hz * = 4 * 2^15 / 32768Hz = 4.00 s * Window0 Closed Period = (WWDT Period) * (Window0 Closed Percent) * = 4.00 s * 12% = 500.00 ms * Window1 Closed Period = (WWDT Period) * (Window1 Closed Percent) * = 4.00 s * 0% = 0.00 s */ DL_WWDT_initWatchdogMode(WWDT0_INST, DL_WWDT_CLOCK_DIVIDE_4, DL_WWDT_TIMER_PERIOD_15_BITS, DL_WWDT_RUN_IN_SLEEP, DL_WWDT_WINDOW_PERIOD_12, DL_WWDT_WINDOW_PERIOD_0); /* Set Window0 as active window */ DL_WWDT_setActiveWindow(WWDT0_INST, DL_WWDT_WINDOW0); } static const DL_MCAN_ClockConfig gMCAN0ClockConf = { .clockSel = DL_MCAN_FCLK_SYSPLLCLK1, .divider = DL_MCAN_FCLK_DIV_1, }; static const DL_MCAN_InitParams gMCAN0InitParams= { /* Initialize MCAN Init parameters. */ .fdMode = false, .brsEnable = false, .txpEnable = true, .efbi = false, .pxhddisable = false, .darEnable = false, .wkupReqEnable = true, .autoWkupEnable = true, .emulationEnable = true, .tdcEnable = true, .wdcPreload = 255, /* Transmitter Delay Compensation parameters. */ .tdcConfig.tdcf = 10, .tdcConfig.tdco = 6, }; static const DL_MCAN_ConfigParams gMCAN0ConfigParams={ /* Initialize MCAN Config parameters. */ .monEnable = false, .asmEnable = false, .tsPrescalar = 15, .tsSelect = 0, .timeoutSelect = DL_MCAN_TIMEOUT_SELECT_CONT, .timeoutPreload = 65535, .timeoutCntEnable = false, .filterConfig.rrfs = false, .filterConfig.rrfe = false, .filterConfig.anfe = 0, .filterConfig.anfs = 0, }; static const DL_MCAN_MsgRAMConfigParams gMCAN0MsgRAMConfigParams ={ /* Standard ID Filter List Start Address. */ .flssa = MCAN0_INST_MCAN_STD_ID_FILT_START_ADDR, /* List Size: Standard ID. */ .lss = MCAN0_INST_MCAN_STD_ID_FILTER_NUM, /* Extended ID Filter List Start Address. */ .flesa = MCAN0_INST_MCAN_EXT_ID_FILT_START_ADDR, /* List Size: Extended ID. */ .lse = MCAN0_INST_MCAN_EXT_ID_FILTER_NUM, /* Tx Buffers Start Address. */ .txStartAddr = MCAN0_INST_MCAN_TX_BUFF_START_ADDR, /* Number of Dedicated Transmit Buffers. */ .txBufNum = MCAN0_INST_MCAN_TX_BUFF_SIZE, .txFIFOSize = 32, /* Tx Buffer Element Size. */ .txBufMode = 0, .txBufElemSize = DL_MCAN_ELEM_SIZE_8BYTES, /* Tx Event FIFO Start Address. */ .txEventFIFOStartAddr = MCAN0_INST_MCAN_TX_EVENT_START_ADDR, /* Event FIFO Size. */ .txEventFIFOSize = MCAN0_INST_MCAN_TX_EVENT_SIZE, /* Level for Tx Event FIFO watermark interrupt. */ .txEventFIFOWaterMark = 25, /* Rx FIFO0 Start Address. */ .rxFIFO0startAddr = MCAN0_INST_MCAN_FIFO_0_START_ADDR, /* Number of Rx FIFO elements. */ .rxFIFO0size = MCAN0_INST_MCAN_FIFO_0_NUM, /* Rx FIFO0 Watermark. */ .rxFIFO0waterMark = 25, .rxFIFO0OpMode = 0, /* Rx FIFO1 Start Address. */ .rxFIFO1startAddr = MCAN0_INST_MCAN_FIFO_1_START_ADDR, /* Number of Rx FIFO elements. */ .rxFIFO1size = MCAN0_INST_MCAN_FIFO_1_NUM, /* Level for Rx FIFO 1 watermark interrupt. */ .rxFIFO1waterMark = 25, /* FIFO blocking mode. */ .rxFIFO1OpMode = 0, /* Rx Buffer Start Address. */ .rxBufStartAddr = MCAN0_INST_MCAN_RX_BUFF_START_ADDR, /* Rx Buffer Element Size. */ .rxBufElemSize = DL_MCAN_ELEM_SIZE_8BYTES, /* Rx FIFO0 Element Size. */ .rxFIFO0ElemSize = DL_MCAN_ELEM_SIZE_8BYTES, /* Rx FIFO1 Element Size. */ .rxFIFO1ElemSize = DL_MCAN_ELEM_SIZE_8BYTES, }; static const DL_MCAN_BitTimingParams gMCAN0BitTimes = { /* Arbitration Baud Rate Pre-scaler. */ .nomRatePrescalar = 0, /* Arbitration Time segment before sample point. */ .nomTimeSeg1 = 124, /* Arbitration Time segment after sample point. */ .nomTimeSeg2 = 17, /* Arbitration (Re)Synchronization Jump Width Range. */ .nomSynchJumpWidth = 17, /* Data Baud Rate Pre-scaler. */ .dataRatePrescalar = 0, /* Data Time segment before sample point. */ .dataTimeSeg1 = 0, /* Data Time segment after sample point. */ .dataTimeSeg2 = 0, /* Data (Re)Synchronization Jump Width. */ .dataSynchJumpWidth = 0, }; SYSCONFIG_WEAK void SYSCFG_DL_MCAN0_init(void) { DL_MCAN_RevisionId revid_MCAN0; DL_MCAN_enableModuleClock(MCAN0_INST); DL_MCAN_setClockConfig(MCAN0_INST, (DL_MCAN_ClockConfig *) &gMCAN0ClockConf); /* Get MCANSS Revision ID. */ DL_MCAN_getRevisionId(MCAN0_INST, &revid_MCAN0); /* Wait for Memory initialization to be completed. */ while(false == DL_MCAN_isMemInitDone(MCAN0_INST)); /* Put MCAN in SW initialization mode. */ DL_MCAN_setOpMode(MCAN0_INST, DL_MCAN_OPERATION_MODE_SW_INIT); /* Wait till MCAN is not initialized. */ while (DL_MCAN_OPERATION_MODE_SW_INIT != DL_MCAN_getOpMode(MCAN0_INST)); /* Initialize MCAN module. */ DL_MCAN_init(MCAN0_INST, (DL_MCAN_InitParams *) &gMCAN0InitParams); /* Configure MCAN module. */ DL_MCAN_config(MCAN0_INST, (DL_MCAN_ConfigParams*) &gMCAN0ConfigParams); /* Configure Bit timings. */ DL_MCAN_setBitTime(MCAN0_INST, (DL_MCAN_BitTimingParams*) &gMCAN0BitTimes); /* Configure Message RAM Sections */ DL_MCAN_msgRAMConfig(MCAN0_INST, (DL_MCAN_MsgRAMConfigParams*) &gMCAN0MsgRAMConfigParams); /* Set Extended ID Mask. */ DL_MCAN_setExtIDAndMask(MCAN0_INST, MCAN0_INST_MCAN_EXT_ID_AND_MASK ); /* Loopback mode */ /* Take MCAN out of the SW initialization mode */ DL_MCAN_setOpMode(MCAN0_INST, DL_MCAN_OPERATION_MODE_NORMAL); while (DL_MCAN_OPERATION_MODE_NORMAL != DL_MCAN_getOpMode(MCAN0_INST)); /* Enable MCAN mopdule Interrupts */ DL_MCAN_enableIntr(MCAN0_INST, MCAN0_INST_MCAN_INTERRUPTS, 1U); DL_MCAN_selectIntrLine(MCAN0_INST, DL_MCAN_INTR_MASK_ALL, DL_MCAN_INTR_LINE_NUM_1); DL_MCAN_enableIntrLine(MCAN0_INST, DL_MCAN_INTR_LINE_NUM_1, 1U); /* Enable MSPM0 MCAN interrupt */ DL_MCAN_clearInterruptStatus(MCAN0_INST,(DL_MCAN_MSP_INTERRUPT_LINE1)); DL_MCAN_enableInterrupt(MCAN0_INST,(DL_MCAN_MSP_INTERRUPT_LINE1)); }