hwsetup.c 45 KB

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  1. /************************************************************************
  2. Project: Welling Motor Control Paltform
  3. Filename: hwsetup.c
  4. Partner Filename: hwsetup.h
  5. Description: Hardware setup
  6. Complier: IAR Embedded Workbench for ARM 7.80.4
  7. CPU TYPE : STM32F30x
  8. *************************************************************************
  9. Copyright (c) 2018 Welling Motor Technology(Shanghai) Co. Ltd.
  10. All rights reserved.
  11. *************************************************************************
  12. *************************************************************************
  13. Revising History (ECL of this file):
  14. ************************************************************************/
  15. /************************************************************************
  16. Beginning of File, do not put anything above here except notes
  17. Compiler Directives:
  18. *************************************************************************/
  19. #ifndef _HWSETUP_C_
  20. #define _HWSETUP_C_
  21. #endif
  22. /************************************************************************
  23. Included File
  24. *************************************************************************/
  25. #include "syspar.h"
  26. #include "user.h"
  27. #include "FuncLayerAPI.h"
  28. //#include "at32f421_wk_config.h"
  29. //#include "at32f421_misc.h"
  30. #include "ti_msp_dl_config.h"
  31. /************************************************************************
  32. Constant Table (N/A)
  33. *************************************************************************/
  34. //#define UART_HMI_BAUD_RATE (1200)
  35. #define UART_HMI_IBRD_36_MHZ_1200_BAUD (1875)
  36. #define UART_HMI_FBRD_36_MHZ_1200_BAUD (0)
  37. /*************************************************************************
  38. Exported Functions:
  39. *************************************************************************/
  40. /*************************************************************************
  41. Function: hw_voHardwareSetup;
  42. Description: Hardware Setup function.
  43. Call by: main();
  44. Input Variables: All HW registers
  45. Output/Return Variables: All HW registers
  46. Subroutine Call: ...;
  47. Reference: N/A
  48. *************************************************************************/
  49. void hw_voHardwareSetup1(void)
  50. {
  51. // Initialize System Control registers, WatchDog to a know state
  52. hw_voInitSysCtrl();
  53. // Select GPIO for the device or for the specific application:
  54. // wk_gpio_config();//
  55. hw_voInitGPIO();
  56. }
  57. void hw_voHardwareSetup2(void)
  58. {
  59. // Initialize all the Device Peripherals to a known state:外设配置
  60. hw_voInitPeri();
  61. // Initialize interrupt priority of peripherals: 中断优先级
  62. hw_voInitInt();
  63. }
  64. /*************************************************************************
  65. Local Functions (N/A)
  66. *************************************************************************/
  67. /*************************************************************************
  68. Function: hw_voInitPWM;
  69. Description: MTU Setup function.
  70. Call by: main();
  71. Input Variables: MTU HW registers
  72. Output/Return Variables: MTU HW registers
  73. Subroutine Call: ...;
  74. Reference: N/A
  75. *************************************************************************/
  76. void hw_voInitPeri(void)
  77. {
  78. // Initialize DMA
  79. hw_voInitDMA();
  80. // Initialize ADC
  81. hw_voInitADC();
  82. // Initialize Timer1
  83. hw_voInitTim1();
  84. /* init cmp function. */
  85. // wk_cmp_init();
  86. /* init tmr3 function. */
  87. // wk_tmr3_init();
  88. /* init tmr6 function. */
  89. // wk_tmr6_init();
  90. /* init tmr16 function. */
  91. // wk_tmr16_init();
  92. /* init tmr17 function. */
  93. // wk_tmr17_init();
  94. // Initialize SysTick
  95. hw_voInitSysTick();
  96. /* init usart1 function. */
  97. hw_voInitUART1();
  98. /* init exint function. */
  99. #if(EMCDEAL_EN==0)
  100. // wk_exint_config();
  101. #endif
  102. /* init usart2 function. */
  103. #if (SIMULATION == 0)
  104. // hw_voInitUART2();
  105. #endif
  106. #if (UART_ID == 3)
  107. DL_UART_Main_setBaudRateDivisor(UART_HMI_INST, UART_HMI_IBRD_36_MHZ_1200_BAUD, UART_HMI_FBRD_36_MHZ_1200_BAUD);
  108. #endif
  109. }
  110. /*************************************************************************
  111. Function:
  112. Description:
  113. Call by:
  114. Input Variables:
  115. Output/Return Variables:
  116. Subroutine Call:
  117. Reference:
  118. *************************************************************************/
  119. void hw_voInitSysCtrl(void)
  120. {
  121. //system clock config program
  122. // wk_system_clock_config();
  123. //config periph clock
  124. // wk_periph_clock_config();
  125. /* config systick clock source */
  126. // systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8);
  127. }
  128. /*************************************************************************
  129. Function:
  130. Description:
  131. Call by:
  132. Input Variables:
  133. Output/Return Variables:
  134. Subroutine Call:
  135. Reference:
  136. *************************************************************************/
  137. void hw_voInitGPIO(void)
  138. {
  139. // gpio_init_type gpio_init_struct;
  140. //
  141. //
  142. // gpio_default_para_init(&gpio_init_struct);
  143. //
  144. // /* add user code begin tmr1_init 1 */
  145. //
  146. // /* add user code end tmr1_init 1 */
  147. //
  148. // /* configure the tmr1 CH1 pin */
  149. // gpio_init_struct.gpio_pins = PWM_AH_PIN;
  150. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  151. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  152. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  153. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  154. // gpio_init(PWM_AH_GPIO_PORT, &gpio_init_struct);
  155. //
  156. // gpio_pin_mux_config(PWM_AH_GPIO_PORT, GPIO_PINS_SOURCE8, GPIO_MUX_2);
  157. //
  158. // /* configure the tmr1 CH1C pin */
  159. // gpio_init_struct.gpio_pins = PWM_AL_PIN;
  160. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  161. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  162. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  163. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  164. // gpio_init(PWM_AL_GPIO_PORT, &gpio_init_struct);
  165. //
  166. // gpio_pin_mux_config(PWM_AL_GPIO_PORT, GPIO_PINS_SOURCE13, GPIO_MUX_2);
  167. //
  168. // /* configure the tmr1 CH2 pin */
  169. // gpio_init_struct.gpio_pins = PWM_BH_PIN;
  170. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  171. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  172. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  173. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  174. // gpio_init(PWM_BH_GPIO_PORT, &gpio_init_struct);
  175. //
  176. // gpio_pin_mux_config(PWM_BH_GPIO_PORT, GPIO_PINS_SOURCE9, GPIO_MUX_2);
  177. //
  178. // /* configure the tmr1 CH2C pin */
  179. // gpio_init_struct.gpio_pins = PWM_BL_PIN;
  180. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  181. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  182. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  183. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  184. // gpio_init(PWM_BL_GPIO_PORT, &gpio_init_struct);
  185. //
  186. // gpio_pin_mux_config(PWM_BL_GPIO_PORT, GPIO_PINS_SOURCE14, GPIO_MUX_2);
  187. //
  188. // /* configure the tmr1 CH3 pin */
  189. // gpio_init_struct.gpio_pins = PWM_CH_PIN;
  190. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  191. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  192. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  193. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  194. // gpio_init(PWM_CH_GPIO_PORT, &gpio_init_struct);
  195. //
  196. // gpio_pin_mux_config(PWM_CH_GPIO_PORT, GPIO_PINS_SOURCE10, GPIO_MUX_2);
  197. //
  198. // /* configure the tmr1 CH3C pin */
  199. // gpio_init_struct.gpio_pins = PWM_CL_PIN;
  200. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  201. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  202. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  203. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  204. // gpio_init(PWM_CL_GPIO_PORT, &gpio_init_struct);
  205. //
  206. // gpio_pin_mux_config(PWM_CL_GPIO_PORT, GPIO_PINS_SOURCE15, GPIO_MUX_2);
  207. //
  208. // /* configure the tmr1 CH4 pin */
  209. // gpio_init_struct.gpio_pins = GPIO_PINS_11;
  210. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  211. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  212. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  213. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE;
  214. // gpio_init(GPIOA, &gpio_init_struct);
  215. // gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE11, GPIO_MUX_2);
  216. }
  217. /*************************************************************************
  218. Function:
  219. Description:
  220. Call by:
  221. Input Variables:
  222. Output/Return Variables:
  223. Subroutine Call:
  224. Reference:
  225. *************************************************************************/
  226. void hw_voInitDMA(void)
  227. {
  228. // /*=======================================================================
  229. // DMA1 Ch5 for Timer1
  230. // =======================================================================*/
  231. // // DMA_InitTypeDef DMA_InitStructure;
  232. //
  233. //// DMA_DeInit(DMA1_Channel5);
  234. //// DMA_InitStructure.DMA_PeripheralBaseAddr = (ULONG)(&TIM1->DMAR); //澶栬鍦板潃
  235. //// DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
  236. //// DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; //涓嶆墽琛屽璁惧湴鍧�澧為噺鎿嶄綔
  237. //// DMA_InitStructure.DMA_MemoryBaseAddr = (ULONG)hw_uwPWMCmpr;//(pwm_stGenOut.uwNewTIM1COMPR); // 鍐呭瓨鍦板潃
  238. //// DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
  239. //// DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; //鎵ц瀛樺偍鍣ㄥ湴鍧�澧為噺鎿嶄綔
  240. //// DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;//浠庡瓨鍌ㄥ櫒鍒板璁�
  241. //// DMA_InitStructure.DMA_BufferSize = TIM1_DMA_NUM; //6閫氶亾
  242. //// DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; //鎵ц寰幆鎿嶄綔
  243. //// DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; //浼樺厛绾ф渶楂�
  244. //// DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; //
  245. //// DMA_Init(DMA1_Channel5, &DMA_InitStructure);
  246. //// /* Enable DMA1 Channel 5 */
  247. //// //DMA_Cmd(DMA1_Channel5, ENABLE);
  248. //
  249. // wk_dma1_channel5_init();
  250. // wk_dma_channel_config(DMA1_CHANNEL5,(uint32_t)&TMR1->dmadt, (uint32_t)hw_uwPWMCmpr, TIM1_DMA_NUM);
  251. //
  252. // /*=======================================================================
  253. // DMA1 Ch1 for ADC1
  254. // =======================================================================*/
  255. //// DMA_DeInit(DMA1_Channel1);
  256. ////
  257. //// DMA_InitStructure.DMA_PeripheralBaseAddr = (ULONG)(&ADC1->DR);
  258. //// DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
  259. //// DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
  260. //// DMA_InitStructure.DMA_MemoryBaseAddr = (ULONG)(hw_uwADC1);
  261. //// DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
  262. //// DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
  263. //// DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
  264. //// DMA_InitStructure.DMA_BufferSize = ADC1_DMA_NUM;
  265. //// DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
  266. //// DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
  267. //// DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
  268. //// DMA_Init(DMA1_Channel1, &DMA_InitStructure);
  269. //// /* Enable DMA1 Channel1 */
  270. //// DMA_Cmd(DMA1_Channel1, ENABLE);
  271. //wk_dma1_channel1_init();
  272. //wk_dma_channel_config(DMA1_CHANNEL1, (uint32_t)&ADC1->odt, (uint32_t)(hw_uwADC1), ADC1_DMA_NUM);
  273. //dma_channel_enable(DMA1_CHANNEL1, TRUE);
  274. /*=======================================================================
  275. DMA1 Ch3 for UART3 receive
  276. =======================================================================*/
  277. /*=======================================================================
  278. DMA1 Ch2 for UART3 transmission
  279. =======================================================================*/
  280. // DMA_Cmd(DMA1_Channel2, ENABLE);
  281. }
  282. /*************************************************************************
  283. Function:
  284. Description:
  285. Call by:
  286. Input Variables:
  287. Output/Return Variables:
  288. Subroutine Call:
  289. Reference:
  290. *************************************************************************/
  291. void hw_voInitADC(void)
  292. {
  293. // wk_adc1_init();
  294. }
  295. void hw_SetIphaseSample(void)
  296. {
  297. // ADC1->psq_bit.pclen =3-1; //adc_preempt_channel_length_set(ADC1, 3);
  298. //
  299. // ADC1->psq_bit.psn2 = ADC_CHANNEL_0; //閲囨牱閫氶亾1
  300. // ADC1->psq_bit.psn3 = ADC_CHANNEL_1; //閲囨牱閫氶亾2
  301. // ADC1->psq_bit.psn4 = ADC_CHANNEL_3; //閲囨牱閫氶亾3
  302. // adc_preempt_channel_length_set(ADC1, 3);
  303. // adc_preempt_channel_set(ADC1, ADC_CHANNEL_0, 1, ADC_SAMPLETIME_1_5);
  304. // adc_preempt_offset_value_set(ADC1, ADC_PREEMPT_CHANNEL_1, 0x0);
  305. // adc_preempt_channel_set(ADC1, ADC_CHANNEL_1, 2, ADC_SAMPLETIME_1_5);
  306. // adc_preempt_offset_value_set(ADC1, ADC_PREEMPT_CHANNEL_2, 0x0);
  307. // adc_preempt_channel_set(ADC1, ADC_CHANNEL_3, 3, ADC_SAMPLETIME_1_5);
  308. // adc_preempt_offset_value_set(ADC1, ADC_PREEMPT_CHANNEL_3, 0x0);
  309. }
  310. //void hw_SetRdsonSample(adc_channel_select_type adc_channel)
  311. //{
  312. // ADC1->psq_bit.pclen =2-1;//adc_preempt_channel_length_set(ADC1, 2);
  313. //
  314. // ADC1->psq_bit.psn3 = adc_channel; //閲囨牱閫氶亾1
  315. // ADC1->psq_bit.psn4 = ADC_CHANNEL_6; //閲囨牱閫氶亾2 姣嶇嚎鐢垫祦鍊�
  316. //
  317. // adc_preempt_channel_length_set(ADC1, 3);
  318. // adc_preempt_channel_set(ADC1, ADC_CHANNEL_6, 1, ADC_SAMPLETIME_1_5);
  319. // adc_preempt_offset_value_set(ADC1, ADC_PREEMPT_CHANNEL_1, 0x0);
  320. // adc_preempt_channel_set(ADC1, ADC_CHANNEL_0, 2, ADC_SAMPLETIME_1_5);
  321. // adc_preempt_offset_value_set(ADC1, ADC_PREEMPT_CHANNEL_2, 0x0);
  322. // adc_preempt_channel_set(ADC1, ADC_CHANNEL_1, 3, ADC_SAMPLETIME_1_5);
  323. // adc_preempt_offset_value_set(ADC1, ADC_PREEMPT_CHANNEL_3, 0x0);
  324. //}
  325. /*************************************************************************
  326. Function:
  327. Description:OBC
  328. Call by:
  329. Input Variables:
  330. Output/Return Variables:
  331. Subroutine Call:
  332. Reference:
  333. *************************************************************************/
  334. void hw_voInitUART1()
  335. {
  336. // gpio_init_type gpio_init_struct;
  337. //
  338. // /* enable the usart1 and gpio clock */
  339. // crm_periph_clock_enable(CRM_USART1_PERIPH_CLOCK, TRUE);
  340. // crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
  341. //
  342. // gpio_default_para_init(&gpio_init_struct);
  343. //
  344. // /* configure the usart2 tx/rx pin */
  345. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  346. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  347. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  348. // gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
  349. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  350. // gpio_init(GPIOB, &gpio_init_struct);
  351. //
  352. // /* config usart1 iomux */
  353. // gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_0);
  354. // gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_0);
  355. //
  356. //// nvic_irq_enable(USART1_IRQn, 3, 3);
  357. //
  358. // /* configure usart1 param */
  359. // usart_init(USART1, 9600, USART_DATA_8BITS, USART_STOP_1_BIT);
  360. // usart_transmitter_enable(USART1, TRUE);
  361. // usart_receiver_enable(USART1, TRUE);
  362. //// usart_interrupt_enable(USART1, USART_RDBF_INT, TRUE);
  363. //// usart_interrupt_enable(USART1, USART_TDBE_INT, TRUE);
  364. // usart_enable(USART1, TRUE);
  365. }
  366. /*************************************************************************
  367. Function:
  368. Description:BMS
  369. Call by:
  370. Input Variables:
  371. Output/Return Variables:
  372. Subroutine Call:
  373. Reference:
  374. *************************************************************************/
  375. void hw_voInitUART2()
  376. {
  377. // gpio_init_type gpio_init_struct;
  378. //
  379. // /* enable the usart1 and gpio clock */
  380. // crm_periph_clock_enable(CRM_USART2_PERIPH_CLOCK, TRUE);
  381. // crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
  382. //
  383. // gpio_default_para_init(&gpio_init_struct);
  384. //
  385. // gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE14, GPIO_MUX_1);
  386. // gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE15, GPIO_MUX_1);
  387. //
  388. // /* configure the usart2 tx/rx pin */
  389. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  390. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  391. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  392. // gpio_init_struct.gpio_pins = GPIO_PINS_14 | GPIO_PINS_15;
  393. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  394. // gpio_init(GPIOA, &gpio_init_struct);
  395. //
  396. // /* config usart1 iomux */
  397. //// gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE14, GPIO_MUX_1);
  398. //// gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE15, GPIO_MUX_1);
  399. //
  400. //// nvic_irq_enable(USART2_IRQn, 3, 3);
  401. //
  402. // /* configure usart1 param */
  403. // usart_init(USART2, 9600, USART_DATA_8BITS, USART_STOP_1_BIT);
  404. // usart_transmitter_enable(USART2, TRUE);
  405. // usart_receiver_enable(USART2, TRUE);
  406. //// usart_interrupt_enable(USART2, USART_RDBF_INT, TRUE);
  407. //// usart_interrupt_enable(USART2, USART_TDBE_INT, TRUE);
  408. // usart_enable(USART2, TRUE);
  409. }
  410. /*************************************************************************
  411. Function:
  412. Description:
  413. Call by:
  414. Input Variables:
  415. Output/Return Variables:
  416. Subroutine Call:
  417. Reference:
  418. *************************************************************************/
  419. void hw_voInitTim1(void)
  420. {
  421. // tmr_output_config_type tmr_output_struct;
  422. // tmr_brkdt_config_type tmr_brkdt_struct;
  423. //
  424. //// TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
  425. //// TIM_OCInitTypeDef TIM_OCInitStructure;
  426. //// TIM_BDTRInitTypeDef TIM_BDTRInitStructure;
  427. ////
  428. //// TIM_DeInit(TIM1);
  429. ////
  430. //// /* Time Base configuration */
  431. //// TIM_TimeBaseStructure.TIM_Prescaler = 0; // TIMx->PSC 鍒嗛
  432. //// TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_CenterAligned3; // TIMx->CR1 bit5~6鍚戜笂鍚戜笅鍧囪璁剧疆
  433. //// TIM_TimeBaseStructure.TIM_Period = HW_HPWM_PERIOD; //鑷姩閲嶈杞藉瘎瀛樺櫒 TIMx->ARR
  434. //// TIM_TimeBaseStructure.TIM_ClockDivision = 0; //TIMx->CR1 bit8~9 鏃堕挓鍒嗛鍥犲瓙
  435. //// TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;// TIMx->RCR 閲嶅璁℃暟瀵勫瓨鍣�
  436. //// TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
  437. ////------------
  438. // /* configure counter settings */
  439. // tmr_base_init(TMR1, 2249, 0);
  440. // tmr_cnt_dir_set(TMR1, TMR_COUNT_TWO_WAY_3);
  441. // tmr_clock_source_div_set(TMR1, TMR_CLOCK_DIV1);
  442. // tmr_repetition_counter_set(TMR1, 0);
  443. // // tmr_period_buffer_enable(TMR1, TRUE); //鑷姩閲嶈杞介瑁呰浇鍏佽
  444. //
  445. //
  446. //
  447. ////--------
  448. //
  449. // // TIM1->EGR = 0x0001;//event generation Register,Bit0:UG=1
  450. //
  451. // /* Channel 1, 2,3 Configuration in PWM mode */
  452. //// TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2; //TIMx->CCMR1 bit 4~6 pwm2妯″紡锛�
  453. //// TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Disable;//TIMx->CCER bit0 鍏抽棴锛� OC1绂佹杈撳嚭
  454. //// TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Disable;// TIMx->CCER bit2 TIMx->CCER 鍏抽棴锛� OC1N绂佹杈撳嚭
  455. //// TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;//TIMx->CCER bit1 OC1楂樼數骞虫湁鏁�
  456. //// TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High; //TIMx->CCER bit4 OC1N楂樼數骞虫湁鏁堬紱
  457. //// TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Reset;//TIMx->CR2 bit8 OC1杈撳嚭绌洪棽鐘舵��
  458. //// TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;//TIMx->CR2 bit9 杈撳嚭绌洪棽鐘舵��
  459. ////
  460. //// TIM_OCInitStructure.TIM_Pulse = HW_HHPWM_PERIOD; //TIMx_CCR1,OC1棰勮杞藉��
  461. //// TIM_OC1Init(TIM1, &TIM_OCInitStructure);
  462. ////
  463. //// TIM_OCInitStructure.TIM_Pulse = HW_HHPWM_PERIOD;//TIMx_CCR2,OC2棰勮杞藉��
  464. //// TIM_OC2Init(TIM1, &TIM_OCInitStructure);
  465. ////
  466. //// TIM_OCInitStructure.TIM_Pulse = HW_HHPWM_PERIOD;//TIMx_CCR3,OC3棰勮杞藉��
  467. //// TIM_OC3Init(TIM1, &TIM_OCInitStructure);
  468. ////
  469. //// /* CH4 configuration as ADC trigger signal */
  470. //// if(cp_stFlg.CurrentSampleModelSelect == SINGLERESISITANCE)
  471. //// {
  472. //// TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
  473. //// TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
  474. //// TIM_OCInitStructure.TIM_Pulse = HW_HPWM_PERIOD - 5;
  475. //// TIM_OC4Init(TIM1, &TIM_OCInitStructure);
  476. //// }
  477. //// else if(cp_stFlg.CurrentSampleModelSelect == RDSON)
  478. //// {
  479. //// TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
  480. //// TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
  481. //// TIM_OCInitStructure.TIM_Pulse = 1;
  482. //// TIM_OC4Init(TIM1, &TIM_OCInitStructure);
  483. //// }
  484. //// else if(cp_stFlg.CurrentSampleModelSelect == COMBINATION)
  485. //// {
  486. //// TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
  487. //// TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
  488. //// TIM_OCInitStructure.TIM_Pulse = 200;
  489. //// TIM_OC4Init(TIM1, &TIM_OCInitStructure);
  490. //// }
  491. //// else if(cp_stFlg.CurrentSampleModelSelect == DOUBLERESISTANCE)
  492. //// {
  493. //// TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; //TIMx->CCER bit12 杈撳嚭浣胯兘
  494. //// TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; //TIMx->CCER 楂樻湁鏁�
  495. //// TIM_OCInitStructure.TIM_Pulse = 1; //TIMx_CCR4 CC4 姣旇緝鍊硷紝1锛屽湪娉㈣胺澶勯噰闆嗙浉鐢垫祦
  496. //// TIM_OC4Init(TIM1, &TIM_OCInitStructure);
  497. //// }
  498. //// else
  499. //// {}
  500. // //-----------------------
  501. // /* configure channel 1 output settings */
  502. // tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_B;
  503. // tmr_output_struct.oc_output_state = FALSE;
  504. // tmr_output_struct.occ_output_state = FALSE;
  505. // tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  506. // tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  507. // tmr_output_struct.oc_idle_state = FALSE;
  508. // tmr_output_struct.occ_idle_state = FALSE;
  509. // tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_1, &tmr_output_struct);
  510. // tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_1, HW_HHPWM_PERIOD); //OC1棰勮杞藉��
  511. // tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_1, FALSE);
  512. //
  513. // tmr_output_channel_immediately_set(TMR1, TMR_SELECT_CHANNEL_1, FALSE);
  514. //
  515. // /* configure channel 2 output settings */
  516. // tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_B;
  517. // tmr_output_struct.oc_output_state = FALSE;
  518. // tmr_output_struct.occ_output_state = FALSE;
  519. // tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  520. // tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  521. // tmr_output_struct.oc_idle_state = FALSE;
  522. // tmr_output_struct.occ_idle_state = FALSE;
  523. // tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_2, &tmr_output_struct);
  524. // tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_2, HW_HHPWM_PERIOD);//OC1棰勮杞藉��
  525. // tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_2, FALSE);
  526. //
  527. // tmr_output_channel_immediately_set(TMR1, TMR_SELECT_CHANNEL_2, FALSE);
  528. //
  529. // /* configure channel 3 output settings */
  530. // tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_B;
  531. // tmr_output_struct.oc_output_state = FALSE;
  532. // tmr_output_struct.occ_output_state = FALSE;
  533. // tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  534. // tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  535. // tmr_output_struct.oc_idle_state = FALSE;
  536. // tmr_output_struct.occ_idle_state = FALSE;
  537. // tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_3, &tmr_output_struct);
  538. // tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_3, HW_HHPWM_PERIOD);//OC1棰勮杞藉��
  539. // tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_3, FALSE);
  540. //
  541. // tmr_output_channel_immediately_set(TMR1, TMR_SELECT_CHANNEL_3, FALSE);
  542. //
  543. // /* configure channel 4 output settings */
  544. // tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_B;
  545. // tmr_output_struct.oc_output_state = FALSE;
  546. // tmr_output_struct.occ_output_state = FALSE;
  547. // tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  548. // tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  549. // tmr_output_struct.oc_idle_state = FALSE;
  550. // tmr_output_struct.occ_idle_state = FALSE;
  551. // tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_4, &tmr_output_struct);
  552. // tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_4, 108);
  553. // tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_4, FALSE); //杈撳嚭姣旇緝1棰勮杞藉け鑳�
  554. //
  555. // tmr_output_channel_immediately_set(TMR1, TMR_SELECT_CHANNEL_4, FALSE);
  556. //
  557. //
  558. // //-------------------------
  559. // //TIMx->BDTR 鍒硅溅鍜屾鍖哄瘎瀛樺櫒
  560. //// TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable; // bit11 杩愯妯″紡涓嬪綋瀹氭椂鍣ㄤ笉宸ヤ綔鏃讹紝涓�鏃CxE=1鎴朇CxNE=1锛岄鍏堝紑鍚疧C/OCN骞惰緭鍑烘棤鏁堢數骞筹紝鐒跺悗
  561. //// //缃甇C/OCN浣胯兘杈撳嚭淇″彿=1銆�
  562. //// TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable; //bit101 绌洪棽妯″紡涓嬪綋瀹氭椂鍣ㄤ笉宸ヤ綔鏃讹紝涓�鏃CxE=1鎴朇CxNE=1锛� OC/OCN棣栧厛杈撳嚭鍏剁┖闂茬數骞筹紝鐒跺悗
  563. //// // OC/OCN浣胯兘杈撳嚭淇″彿=1銆�
  564. //// TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_2; //閿佸畾绾у埆2
  565. //// TIM_BDTRInitStructure.TIM_DeadTime = cp_stControlPara.swIPMDeadTimeNs / 100 * TIM1CLK_KHZ / 1000 / 10;//bot0~7 姝诲尯浜嬮棿1us
  566. //// TIM_BDTRInitStructure.TIM_Break = TIM_Break_Enable; //bit12 寮�鍚埞杞﹁緭鍏�
  567. //// TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_Low;//bit13 鍒硅溅杈撳叆浣庣數骞虫湁鏁�
  568. //// TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;//bit14 鑷姩杈撳嚭浣胯兘 MOE鍙兘琚蒋浠剁疆鈥�1鈥�
  569. //// TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure);
  570. ////--------------------
  571. // /* configure break and dead-time settings */
  572. // tmr_brkdt_struct.brk_enable = TRUE;//TRUE;//FALSE;//TRUE;
  573. // tmr_brkdt_struct.auto_output_enable = FALSE;
  574. //#if(HARDWAREV30==1)
  575. // tmr_brkdt_struct.brk_polarity =TMR_BRK_INPUT_ACTIVE_HIGH;// TMR_BRK_INPUT_ACTIVE_HIGH;
  576. //#else
  577. // tmr_brkdt_struct.brk_polarity = TMR_BRK_INPUT_ACTIVE_HIGH;//TMR_BRK_INPUT_ACTIVE_LOW;// TMR_BRK_INPUT_ACTIVE_HIGH;
  578. //#endif
  579. // tmr_brkdt_struct.fcsoen_state = TRUE;
  580. // tmr_brkdt_struct.fcsodis_state = TRUE;
  581. // tmr_brkdt_struct.wp_level = TMR_WP_LEVEL_2;
  582. // tmr_brkdt_struct.deadtime = 72;
  583. // tmr_brkdt_config(TMR1, &tmr_brkdt_struct);
  584. // //-------------------
  585. //// TIM_OC1PreloadConfig(TIM1, TIM_OCPreload_Disable);// TIMx->CCMR1 bit3 杈撳嚭姣旇緝1棰勮杞戒娇鑳斤紝闅忔椂鍐欏叆TIMx_CCR1瀵勫瓨鍣紝骞朵笖鏂板啓鍏ョ殑鏁板�肩珛鍗宠捣浣滅敤
  586. //// TIM_OC2PreloadConfig(TIM1, TIM_OCPreload_Disable);//TIMx->CCMR1 bit11
  587. //// TIM_OC3PreloadConfig(TIM1, TIM_OCPreload_Disable);//TIMx->CCMR2 bit3
  588. //// TIM_OC4PreloadConfig(TIM1, TIM_OCPreload_Disable); //TIMx->CCMR2 bit113 Disables the TIM1 peripheral Preload register on CCR4
  589. //// TIM_ARRPreloadConfig(TIM1, ENABLE); //TIMx->CR1 bit7 鑷姩閲嶈杞介瑁呰浇鍏佽浣� Enables TIMx peripheral Preload register on ARR
  590. ////
  591. ////
  592. //// TIM_DMAConfig(TIM1, TIM_DMABase_CCR1, TIM_DMABurstLength_3Transfers);// TIMx->DCR bit0~4 bit8~12 杩炵画浼犻��3涓�氶亾锛孌MA鍩哄湴鍧�TIMx_CR1
  593. ////
  594. ////
  595. //// TIM_SelectMasterSlaveMode(TIM1, TIM_MasterSlaveMode_Enable); //TIMx->SMCR bit7 MSM:1; Master Slave Mode
  596. //// TIM_SelectOutputTrigger(TIM1, TIM_TRGOSource_Update); //TIMx->CR2 bit4~6 涓绘ā寮忛�夋嫨锛屾洿鏂颁簨浠惰閫変负瑙﹀彂杈撳叆(TRGO)
  597. ////
  598. //// /*Main Output ENABLE*/
  599. //// TIM_CtrlPWMOutputs(TIM1, ENABLE); //TIMx->BDTR bit15 MOE 涓昏緭鍑轰娇鑳�
  600. // //------------------
  601. // //tmr_counter_enable(TMR1,TRUE);
  602. // tmr_period_buffer_enable(TMR1, TRUE); //鑷姩閲嶈杞介瑁呰浇鍏佽
  603. // TMR1->dmactrl = 0x0200|TMR_C1DT_ADDRESS; ////DMA1浼犺緭娆℃暟3 锛孴MR_C1DT_ADDRESS
  604. //
  605. //
  606. // /* configure primary mode settings */
  607. // tmr_sub_sync_mode_set(TMR1, TRUE); //娆″畾鏃跺櫒鍚屾
  608. // tmr_primary_mode_select(TMR1, TMR_PRIMARY_SEL_OVERFLOW);//涓诲畾鏃跺櫒杈撳嚭淇″彿閫夋嫨:婧㈠嚭浜嬩欢
  609. //
  610. // tmr_output_enable(TMR1,TRUE);//OEN 涓昏緭鍑轰娇鑳�
  611. //----------------
  612. //
  613. // wk_tmr1_init();
  614. }
  615. /*************************************************************************
  616. Function:
  617. Description:
  618. Call by:
  619. Input Variables:
  620. Output/Return Variables:
  621. Subroutine Call:
  622. Reference:
  623. *************************************************************************/
  624. //void hw_voInitTim2(void)
  625. //{
  626. //
  627. // TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
  628. // TIM_ICInitTypeDef TIM_ICInitStructure;
  629. // TIM_DeInit(TIM2);
  630. //
  631. // /* TIM4 capture of sensor of frequency */
  632. // TIM_TimeBaseStructure.TIM_Prescaler = 0;
  633. // TIM_TimeBaseStructure.TIM_ClockDivision = 0;
  634. // TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
  635. //// TIM_TimeBaseStructure.TIM_Period = FTBC_HZ * 4 / FTBS_HZ - 1;
  636. // TIM_TimeBaseStructure.TIM_Period =TIM2CLK_KHZ * 1000 / FTBS_HZ - 1;
  637. // TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
  638. // TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
  639. //
  640. //// /* Slaves (TIM2) Configuration */
  641. //// TIM_SelectSlaveMode(TIM2, TIM_SlaveMode_External1);
  642. //// /* Selects the Input Trigger source */
  643. //// TIM_SelectInputTrigger(TIM2, TIM_TS_ITR0); // IRT0锟斤拷TIM1
  644. //
  645. // TIM_ARRPreloadConfig(TIM2, ENABLE); // Enables TIMx peripheral Preload register on ARR
  646. // //TIM_SelectMasterSlaveMode(TIM2, TIM_MasterSlaveMode_Enable); // MSM:1; Master Slave Mode
  647. //
  648. // TIM_ICInitStructure.TIM_Channel = TIM_Channel_3;
  649. // TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
  650. // TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
  651. // TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
  652. // TIM_ICInitStructure.TIM_ICFilter = 0;
  653. // TIM_ICInit(TIM2, &TIM_ICInitStructure);
  654. //
  655. // TIM_ICInitStructure.TIM_Channel = TIM_Channel_4;
  656. // TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
  657. // TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
  658. // TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
  659. // TIM_ICInitStructure.TIM_ICFilter = 0;
  660. // TIM_ICInit(TIM2, &TIM_ICInitStructure);
  661. //}
  662. /*************************************************************************
  663. Function:
  664. Description:
  665. Call by:
  666. Input Variables:
  667. Output/Return Variables:
  668. Subroutine Call:
  669. Reference:
  670. *************************************************************************/
  671. //void hw_voInitTim3(void)
  672. //{
  673. //
  674. // TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
  675. // TIM_ICInitTypeDef TIM_ICInitStructure;
  676. //
  677. // TIM_DeInit(TIM3);
  678. //
  679. // /* TIM3 capture of sensor of frequency */
  680. // TIM_TimeBaseStructure.TIM_Prescaler = 19; // TIMx_PSC, Counter clock frequency = fCK_PSC/(PSC[15:0]+1)
  681. // TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
  682. // TIM_TimeBaseStructure.TIM_Period = 60000; //[15:0] Maximum count value 65535
  683. // TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
  684. // TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
  685. // TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
  686. //
  687. // /* Hall IC Signal */
  688. // TIM_ICInitStructure.TIM_Channel = TIM_Channel_1;
  689. // TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
  690. // TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
  691. // TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
  692. // TIM_ICInitStructure.TIM_ICFilter = 0x0;
  693. // TIM_ICInit(TIM3, &TIM_ICInitStructure);
  694. //
  695. // TIM_ICInitStructure.TIM_Channel = TIM_Channel_2;
  696. // TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
  697. // TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
  698. // TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
  699. // TIM_ICInitStructure.TIM_ICFilter = 0x0;
  700. // TIM_ICInit(TIM3, &TIM_ICInitStructure);
  701. //
  702. // TIM_ICInitStructure.TIM_Channel = TIM_Channel_3;
  703. // TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
  704. // TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
  705. // TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
  706. // TIM_ICInitStructure.TIM_ICFilter = 0x0;
  707. // TIM_ICInit(TIM3, &TIM_ICInitStructure);
  708. //
  709. // TIM_ARRPreloadConfig(TIM3, ENABLE); // Enables TIMx peripheral Preload register on ARR
  710. //
  711. //}
  712. /*************************************************************************
  713. Function:
  714. Description:
  715. Call by:
  716. Input Variables:
  717. Output/Return Variables:
  718. Subroutine Call:
  719. Reference:
  720. *************************************************************************/
  721. //void hw_voInitTim4(void)
  722. //{
  723. // TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
  724. // TIM_DeInit(TIM4);
  725. //
  726. // TIM_TimeBaseStructure.TIM_Prescaler = 0;
  727. // TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
  728. // TIM_TimeBaseStructure.TIM_Period = APB2CLK_KHZ * 1000 / FPWM_HZ * 2; //HW_PWM_PERIOD * 2;
  729. // TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
  730. // TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
  731. // TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
  732. //
  733. // TIM_ARRPreloadConfig(TIM4, ENABLE); // Enables TIMx peripheral Preload register on ARR
  734. //}
  735. /*************************************************************************
  736. Function:
  737. Description:
  738. Call by:
  739. Input Variables:
  740. Output/Return Variables:
  741. Subroutine Call:
  742. Reference:
  743. *************************************************************************/
  744. /*************************************************************************
  745. Function:
  746. Description:
  747. Call by:
  748. Input Variables:
  749. Output/Return Variables:
  750. Subroutine Call:
  751. Reference:
  752. *************************************************************************/
  753. void hw_voInitSysTick(void)
  754. {
  755. /* Setup systick timer interrupts */
  756. //SysTick_Config(SystemCoreClock / FSYSTICK_HZ);
  757. // systick_interrupt_config(system_core_clock / 8 / 1000);
  758. }
  759. /*************************************************************************
  760. Function:
  761. Description:
  762. Call by:
  763. Input Variables:
  764. Output/Return Variables:
  765. Subroutine Call:
  766. Reference: 浼樺厛绾�
  767. *************************************************************************/
  768. void hw_voInitInt(void)
  769. {
  770. // NVIC_InitTypeDef NVIC_InitStructure;
  771. //
  772. // NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
  773. //
  774. // /* Enable the ADC1,2 Interrupt */
  775. // NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn;
  776. // NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
  777. // NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
  778. // NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  779. // NVIC_Init(&NVIC_InitStructure);
  780. //
  781. // /* Enable the TIM1 Interrupt PWM Interrupt*/
  782. // NVIC_InitStructure.NVIC_IRQChannel = TIM1_UP_IRQn;
  783. // NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
  784. // NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
  785. // NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  786. // NVIC_Init(&NVIC_InitStructure);
  787. //
  788. //
  789. // /* Enable TIM2 Interrupt TIM2 CAP*/
  790. // NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
  791. // NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
  792. // NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
  793. // NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  794. // NVIC_Init(&NVIC_InitStructure);
  795. //
  796. // /* Enable TIM3 Interrupt, TIM3 HALL CAP*/
  797. // NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;
  798. // NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
  799. // NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
  800. // NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  801. // NVIC_Init(&NVIC_InitStructure);
  802. // wk_nvic_config();
  803. }
  804. /*************************************************************************
  805. Function:
  806. Description:
  807. Call by:
  808. Input Variables:
  809. Output/Return Variables:
  810. Subroutine Call:
  811. Reference:涓柇寮�鍚�
  812. *************************************************************************/
  813. void hw_voEnInt(void)
  814. {
  815. // /* ADC group conversion Interrupts enable */
  816. // if(cp_stFlg.CurrentSampleModelSelect== SINGLERESISITANCE)
  817. // {
  818. // ADC_ITConfig(ADC2, ADC_IT_JEOC, ENABLE);
  819. // }
  820. // else if((cp_stFlg.CurrentSampleModelSelect == DOUBLERESISTANCE) || (cp_stFlg.CurrentSampleModelSelect== RDSON))
  821. // {
  822. // ADC_ITConfig(ADC1, ADC_IT_JEOC, ENABLE);
  823. // }
  824. // else if(cp_stFlg.CurrentSampleModelSelect== COMBINATION)
  825. // {
  826. // ADC_ITConfig(ADC1, ADC_IT_JEOC, ENABLE);
  827. // ADC_ITConfig(ADC2, ADC_IT_JEOC, ENABLE);
  828. // }
  829. // else
  830. // {
  831. //
  832. // }
  833. //
  834. // /* TIM1 Interrupts enable */
  835. // TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE);
  836. //// TIM_ITConfig(TIM1, TIM_IT_CC4, ENABLE);
  837. //
  838. // /* TIM2 Interrupts enable */
  839. // TIM_ITConfig(TIM2, TIM_IT_CC3, ENABLE);
  840. // TIM_ITConfig(TIM2, TIM_IT_CC4, ENABLE);
  841. // TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);
  842. //
  843. // /* TIM3 Interrupts enable */
  844. // TIM_ITConfig(TIM3, TIM_IT_Update, ENABLE);
  845. // TIM_ITConfig(TIM3, TIM_IT_CC1, ENABLE);
  846. // TIM_ITConfig(TIM3, TIM_IT_CC2, ENABLE);
  847. // TIM_ITConfig(TIM3, TIM_IT_CC3, ENABLE);
  848. //
  849. // /* DMA full transfer finish interrupt */
  850. // DMA_ITConfig(DMA1_Channel2, DMA_IT_TC, ENABLE);
  851. // DMA_ITConfig(DMA1_Channel3, DMA_IT_TC, ENABLE);
  852. //--------------------
  853. /* add user code begin adc1_init 2 */
  854. //adc_interrupt_enable(ADC1,ADC_CCE_INT,TRUE);
  855. // adc_interrupt_enable(ADC1,ADC_PCCE_INT,TRUE);
  856. //// dma_interrupt_enable(DMA1_CHANNEL1,DMA_FDT_INT,TRUE);
  857. //
  858. // /* add user code begin tmr1_init 2 */
  859. // tmr_interrupt_enable(TMR1,TMR_OVF_INT,TRUE);
  860. // tmr_flag_clear(TMR1,TMR_BRK_FLAG);
  861. // tmr_interrupt_enable(TMR1,TMR_BRK_INT,TRUE);
  862. //
  863. // // (TMR16,TMR_C1_INT,TRUE);
  864. // tmr_flag_clear(TMR16, TMR_C1_INT | TMR_OVF_INT );
  865. // tmr_interrupt_enable(TMR16,TMR_OVF_INT,TRUE);
  866. // tmr_interrupt_enable(TMR16,TMR_C1_INT,TRUE);
  867. //
  868. // // (TMR17,TMR_C1_INT,TRUE);
  869. // tmr_flag_clear(TMR17, TMR_C1_INT | TMR_OVF_INT );
  870. // tmr_interrupt_enable(TMR17,TMR_OVF_INT,TRUE);
  871. // tmr_interrupt_enable(TMR17,TMR_C1_INT,TRUE);
  872. // //------time3
  873. // tmr_flag_clear(TMR3, TMR_C1_INT | TMR_OVF_INT |TMR_C2_INT |TMR_C3_INT);
  874. // tmr_interrupt_enable(TMR3, TMR_C1_INT, TRUE);
  875. // tmr_interrupt_enable(TMR3, TMR_C2_INT, TRUE);
  876. // tmr_interrupt_enable(TMR3, TMR_C3_INT, TRUE);
  877. // tmr_interrupt_enable(TMR3, TMR_OVF_INT, TRUE);
  878. //
  879. // usart_interrupt_enable(USART1, USART_RDBF_INT, TRUE);
  880. // usart_interrupt_enable(USART1, USART_TDBE_INT, TRUE);
  881. //
  882. //#if (SIMULATION == 0)
  883. // usart_interrupt_enable(USART2, USART_RDBF_INT, TRUE);
  884. // usart_interrupt_enable(USART2, USART_TDBE_INT, TRUE);
  885. //#endif
  886. }
  887. /*************************************************************************
  888. Function:
  889. Description:
  890. Call by:
  891. Input Variables:
  892. Output/Return Variables:
  893. Subroutine Call:
  894. Reference:寮�鍚鏁�
  895. *************************************************************************/
  896. void hw_voTimEn(void)
  897. {
  898. // tmr_counter_enable(TMR1, TRUE);
  899. // tmr_counter_enable(TMR3, TRUE);
  900. // tmr_counter_enable(TMR6, TRUE);
  901. // tmr_counter_enable(TMR16, TRUE);
  902. // tmr_counter_enable(TMR17, TRUE);
  903. // /* TIM1 counter enable */
  904. // TIM_Cmd(TIM1, ENABLE);
  905. // /* TIM2 counter enable */
  906. // TIM_Cmd(TIM2, ENABLE);
  907. // /* TIM3 counter enable */
  908. // TIM_Cmd(TIM3, ENABLE);
  909. // /* TIM4 counter enable */
  910. // TIM_Cmd(TIM4, ENABLE);
  911. // DL_TimerA_startCounter(MOTOR_PWM_INST);
  912. }
  913. /*************************************************************************
  914. Function:
  915. Description:
  916. Call by:
  917. Input Variables:
  918. Output/Return Variables:
  919. Subroutine Call:
  920. Reference:pwm鍒濆鍖�
  921. *************************************************************************/
  922. void hw_voPWMInit(void)
  923. {
  924. /* Set 50% duty */
  925. pwm_stGenOut.uwNewTIM1COMPR[0] = HW_HHPWM_PERIOD;
  926. pwm_stGenOut.uwNewTIM1COMPR[1] = HW_HHPWM_PERIOD;
  927. pwm_stGenOut.uwNewTIM1COMPR[2] = HW_HHPWM_PERIOD;
  928. pwm_stGenOut.uwNewTIM1COMPR[3] = HW_HHPWM_PERIOD;
  929. pwm_stGenOut.uwNewTIM1COMPR[4] = HW_HHPWM_PERIOD;
  930. pwm_stGenOut.uwNewTIM1COMPR[5] = HW_HHPWM_PERIOD;
  931. /* PWM off */
  932. hw_voPWMOff();
  933. /* Charge init */
  934. hw_uwChrgCt = 0;
  935. hw_blChrgOvrFlg = FALSE;
  936. }
  937. /*************************************************************************
  938. Function:
  939. Description:
  940. Call by:
  941. Input Variables:
  942. Output/Return Variables:
  943. Subroutine Call:
  944. Reference:寮�椹卞姩
  945. *************************************************************************/
  946. void hw_voPWMOn(void)
  947. {
  948. if (hw_blPWMOnFlg == FALSE)
  949. {
  950. // /* CH1, CH2 set to "PWM mode 2" */
  951. // TMR1->cm1 |= 0x7070;// TIM1->CCMR1 |= 0x7070;
  952. // /* CH3 set to "PWM mode 2" */
  953. // TMR1->cm2 |= 0x7070;// TIM1->CCMR2 |= 0x7070;
  954. // /* CH1, CH2 and CH3 output enable */
  955. // TMR1->cctrl |= 0x5555;// TIM1->CCER |= 0x5555; 楂樻湁鏁�
  956. //// TIM1->CCER |= 0x0FFF;
  957. //
  958. // /* Flag set */
  959. DL_Timer_overrideCCPOut(MOTOR_PWM_INST, DL_TIMER_FORCE_OUT_DISABLED, DL_TIMER_FORCE_CMPL_OUT_DISABLED, DL_TIMER_CC_0_INDEX);
  960. DL_Timer_overrideCCPOut(MOTOR_PWM_INST, DL_TIMER_FORCE_OUT_DISABLED, DL_TIMER_FORCE_CMPL_OUT_DISABLED, DL_TIMER_CC_1_INDEX);
  961. DL_Timer_overrideCCPOut(MOTOR_PWM_INST, DL_TIMER_FORCE_OUT_DISABLED, DL_TIMER_FORCE_CMPL_OUT_DISABLED, DL_TIMER_CC_2_INDEX);
  962. hw_blPWMOnFlg = TRUE;
  963. }
  964. }
  965. /*************************************************************************
  966. Function:
  967. Description:
  968. Call by:
  969. Input Variables:
  970. Output/Return Variables:
  971. Subroutine Call:
  972. Reference:鍏抽┍鍔�
  973. *************************************************************************/
  974. void hw_voPWMOff(void)
  975. {
  976. if (hw_blPWMOnFlg == TRUE)
  977. {
  978. // /* CH1, CH2 set to "Frozen" */
  979. // TMR1->cm1 &= ~0x7070;// TIM1->CCMR1 &= ~0x7070;
  980. // /* CH3 set to "Frozen" */
  981. //// TIM1->CCMR2 &= ~0x7070;
  982. // TMR1->cm2&= ~0x0070; // TIM1->CCMR2 &= ~0x0070; //don't change CC4
  983. // /* CH1, CH2 set to "Force inactive level" */
  984. // TMR1->cm1 |= 0x4040;// TIM1->CCMR1 |= 0x4040;
  985. // /* CH3 set to "Force inactive level" */
  986. //// TIM1->CCMR2 |= 0x4040;
  987. // TMR1->cm2 |= 0x0040; // TIM1->CCMR2 |= 0x0040; //don't change CC4
  988. // /* CH1, CH2 and CH3 complementary output disable */
  989. //// TIM1->CCER &= ~0x4444;
  990. // TMR1->cctrl &= ~0x4444;//TIM1->CCER &= ~0x4444;
  991. //
  992. DL_Timer_overrideCCPOut(MOTOR_PWM_INST, DL_TIMER_FORCE_OUT_LOW, DL_TIMER_FORCE_CMPL_OUT_LOW, DL_TIMER_CC_0_INDEX);
  993. DL_Timer_overrideCCPOut(MOTOR_PWM_INST, DL_TIMER_FORCE_OUT_LOW, DL_TIMER_FORCE_CMPL_OUT_LOW, DL_TIMER_CC_1_INDEX);
  994. DL_Timer_overrideCCPOut(MOTOR_PWM_INST, DL_TIMER_FORCE_OUT_LOW, DL_TIMER_FORCE_CMPL_OUT_LOW, DL_TIMER_CC_2_INDEX);
  995. /* Flag set */
  996. hw_blPWMOnFlg = FALSE;
  997. }
  998. }
  999. /*************************************************************************
  1000. Function:
  1001. Description:
  1002. Call by:
  1003. Input Variables:
  1004. Output/Return Variables:
  1005. Subroutine Call:
  1006. Reference:50%鍗犵┖姣旇嚜妫�
  1007. *************************************************************************/
  1008. void hw_voCharge(void)
  1009. {
  1010. /* Set 50% duty */
  1011. pwm_stGenOut.uwNewTIM1COMPR[0] = HW_HHPWM_PERIOD;
  1012. pwm_stGenOut.uwNewTIM1COMPR[1] = HW_HHPWM_PERIOD;
  1013. pwm_stGenOut.uwNewTIM1COMPR[2] = HW_HHPWM_PERIOD;
  1014. pwm_stGenOut.uwNewTIM1COMPR[3] = HW_HHPWM_PERIOD;
  1015. pwm_stGenOut.uwNewTIM1COMPR[4] = HW_HHPWM_PERIOD;
  1016. pwm_stGenOut.uwNewTIM1COMPR[5] = HW_HHPWM_PERIOD;
  1017. // pwm_stGenOut.uwNewTIM1COMPR[0] = 337;
  1018. // pwm_stGenOut.uwNewTIM1COMPR[1] = HW_HHPWM_PERIOD;
  1019. // pwm_stGenOut.uwNewTIM1COMPR[2] = HW_HHPWM_PERIOD;
  1020. // pwm_stGenOut.uwNewTIM1COMPR[3] = 337;
  1021. // pwm_stGenOut.uwNewTIM1COMPR[4] = HW_HHPWM_PERIOD;
  1022. // pwm_stGenOut.uwNewTIM1COMPR[5] = HW_HHPWM_PERIOD;
  1023. /* PWM on */
  1024. hw_voPWMOn();
  1025. if (++hw_uwChrgCt > cp_stControlPara.swIPMHvicChrgMs)
  1026. {
  1027. hw_uwChrgCt = 0;
  1028. hw_blChrgOvrFlg = TRUE;
  1029. }
  1030. }
  1031. /* Three phase short */
  1032. /*************************************************************************
  1033. Function:
  1034. Description:
  1035. Call by:
  1036. Input Variables:
  1037. Output/Return Variables:
  1038. Subroutine Call:
  1039. Reference:
  1040. *************************************************************************/
  1041. void hw_voThrPhsShrt(void)
  1042. {
  1043. /* Set 0% duty */
  1044. pwm_stGenOut.uwNewTIM1COMPR[0] = HW_HPWM_PERIOD;
  1045. pwm_stGenOut.uwNewTIM1COMPR[1] = HW_HPWM_PERIOD;
  1046. pwm_stGenOut.uwNewTIM1COMPR[2] = HW_HPWM_PERIOD;
  1047. pwm_stGenOut.uwNewTIM1COMPR[3] = HW_HPWM_PERIOD;
  1048. pwm_stGenOut.uwNewTIM1COMPR[4] = HW_HPWM_PERIOD;
  1049. pwm_stGenOut.uwNewTIM1COMPR[5] = HW_HPWM_PERIOD;
  1050. pwm_stGenOut.uwFirstTrigCOMPR = HW_HHHPWM_PERIOD;
  1051. pwm_stGenOut.uwSecondTrigCOMPR = HW_HPWM_PERIOD - HW_HHHPWM_PERIOD;
  1052. /* PWM on */
  1053. hw_voPWMOn();
  1054. }
  1055. /*************************************************************************
  1056. Function
  1057. Description: Initialize UART
  1058. Call by: ;
  1059. Input Variables: N/A
  1060. Output/Return Variables: N/A
  1061. Subroutine Call: ...;
  1062. Reference: N/A鐪嬮棬鐙�
  1063. ****************************************************************/
  1064. void hw_voIWDGInit(UWORD prer, UWORD rlr)
  1065. {
  1066. // RCC_LSICmd(ENABLE);
  1067. // while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) != SET)
  1068. // {}
  1069. // IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
  1070. // IWDG_SetPrescaler(prer);
  1071. // IWDG_SetReload(rlr);
  1072. // IWDG_ReloadCounter();
  1073. // IWDG_Enable();
  1074. }
  1075. /*************************************************************************
  1076. Copyright (c) 2018 Welling Motor Technology(Shanghai) Co. Ltd.
  1077. All rights reserved.
  1078. *************************************************************************/
  1079. #ifdef _HWSETUP_C_
  1080. #undef _HWSETUP_C_
  1081. #endif
  1082. /************************************************************************
  1083. End of this File (EOF)!
  1084. Do not put anything after this part!
  1085. *************************************************************************/