hwsetup.c 44 KB

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  1. /************************************************************************
  2. Project: Welling Motor Control Paltform
  3. Filename: hwsetup.c
  4. Partner Filename: hwsetup.h
  5. Description: Hardware setup
  6. Complier: IAR Embedded Workbench for ARM 7.80.4
  7. CPU TYPE : STM32F30x
  8. *************************************************************************
  9. Copyright (c) 2018 Welling Motor Technology(Shanghai) Co. Ltd.
  10. All rights reserved.
  11. *************************************************************************
  12. *************************************************************************
  13. Revising History (ECL of this file):
  14. ************************************************************************/
  15. /************************************************************************
  16. Beginning of File, do not put anything above here except notes
  17. Compiler Directives:
  18. *************************************************************************/
  19. #ifndef _HWSETUP_C_
  20. #define _HWSETUP_C_
  21. #endif
  22. /************************************************************************
  23. Included File
  24. *************************************************************************/
  25. #include "syspar.h"
  26. #include "user.h"
  27. #include "FuncLayerAPI.h"
  28. //#include "at32f421_wk_config.h"
  29. //#include "at32f421_misc.h"
  30. #include "ti_msp_dl_config.h"
  31. /************************************************************************
  32. Constant Table (N/A)
  33. *************************************************************************/
  34. /*************************************************************************
  35. Exported Functions:
  36. *************************************************************************/
  37. /*************************************************************************
  38. Function: hw_voHardwareSetup;
  39. Description: Hardware Setup function.
  40. Call by: main();
  41. Input Variables: All HW registers
  42. Output/Return Variables: All HW registers
  43. Subroutine Call: ...;
  44. Reference: N/A
  45. *************************************************************************/
  46. void hw_voHardwareSetup1(void)
  47. {
  48. // Initialize System Control registers, WatchDog to a know state
  49. hw_voInitSysCtrl();
  50. // Select GPIO for the device or for the specific application:
  51. // wk_gpio_config();//
  52. hw_voInitGPIO();
  53. }
  54. void hw_voHardwareSetup2(void)
  55. {
  56. // Initialize all the Device Peripherals to a known state:外设配置
  57. hw_voInitPeri();
  58. // Initialize interrupt priority of peripherals: 中断优先级
  59. hw_voInitInt();
  60. }
  61. /*************************************************************************
  62. Local Functions (N/A)
  63. *************************************************************************/
  64. /*************************************************************************
  65. Function: hw_voInitPWM;
  66. Description: MTU Setup function.
  67. Call by: main();
  68. Input Variables: MTU HW registers
  69. Output/Return Variables: MTU HW registers
  70. Subroutine Call: ...;
  71. Reference: N/A
  72. *************************************************************************/
  73. void hw_voInitPeri(void)
  74. {
  75. // Initialize DMA
  76. hw_voInitDMA();
  77. // Initialize ADC
  78. hw_voInitADC();
  79. // Initialize Timer1
  80. hw_voInitTim1();
  81. /* init cmp function. */
  82. // wk_cmp_init();
  83. /* init tmr3 function. */
  84. // wk_tmr3_init();
  85. /* init tmr6 function. */
  86. // wk_tmr6_init();
  87. /* init tmr16 function. */
  88. // wk_tmr16_init();
  89. /* init tmr17 function. */
  90. // wk_tmr17_init();
  91. // Initialize SysTick
  92. hw_voInitSysTick();
  93. /* init usart1 function. */
  94. hw_voInitUART1();
  95. /* init exint function. */
  96. #if(EMCDEAL_EN==0)
  97. // wk_exint_config();
  98. #endif
  99. /* init usart2 function. */
  100. #if (SIMULATION == 0)
  101. hw_voInitUART2();
  102. #endif
  103. }
  104. /*************************************************************************
  105. Function:
  106. Description:
  107. Call by:
  108. Input Variables:
  109. Output/Return Variables:
  110. Subroutine Call:
  111. Reference:
  112. *************************************************************************/
  113. void hw_voInitSysCtrl(void)
  114. {
  115. //system clock config program
  116. // wk_system_clock_config();
  117. //config periph clock
  118. // wk_periph_clock_config();
  119. /* config systick clock source */
  120. // systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8);
  121. }
  122. /*************************************************************************
  123. Function:
  124. Description:
  125. Call by:
  126. Input Variables:
  127. Output/Return Variables:
  128. Subroutine Call:
  129. Reference:
  130. *************************************************************************/
  131. void hw_voInitGPIO(void)
  132. {
  133. // gpio_init_type gpio_init_struct;
  134. //
  135. //
  136. // gpio_default_para_init(&gpio_init_struct);
  137. //
  138. // /* add user code begin tmr1_init 1 */
  139. //
  140. // /* add user code end tmr1_init 1 */
  141. //
  142. // /* configure the tmr1 CH1 pin */
  143. // gpio_init_struct.gpio_pins = PWM_AH_PIN;
  144. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  145. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  146. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  147. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  148. // gpio_init(PWM_AH_GPIO_PORT, &gpio_init_struct);
  149. //
  150. // gpio_pin_mux_config(PWM_AH_GPIO_PORT, GPIO_PINS_SOURCE8, GPIO_MUX_2);
  151. //
  152. // /* configure the tmr1 CH1C pin */
  153. // gpio_init_struct.gpio_pins = PWM_AL_PIN;
  154. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  155. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  156. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  157. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  158. // gpio_init(PWM_AL_GPIO_PORT, &gpio_init_struct);
  159. //
  160. // gpio_pin_mux_config(PWM_AL_GPIO_PORT, GPIO_PINS_SOURCE13, GPIO_MUX_2);
  161. //
  162. // /* configure the tmr1 CH2 pin */
  163. // gpio_init_struct.gpio_pins = PWM_BH_PIN;
  164. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  165. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  166. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  167. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  168. // gpio_init(PWM_BH_GPIO_PORT, &gpio_init_struct);
  169. //
  170. // gpio_pin_mux_config(PWM_BH_GPIO_PORT, GPIO_PINS_SOURCE9, GPIO_MUX_2);
  171. //
  172. // /* configure the tmr1 CH2C pin */
  173. // gpio_init_struct.gpio_pins = PWM_BL_PIN;
  174. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  175. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  176. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  177. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  178. // gpio_init(PWM_BL_GPIO_PORT, &gpio_init_struct);
  179. //
  180. // gpio_pin_mux_config(PWM_BL_GPIO_PORT, GPIO_PINS_SOURCE14, GPIO_MUX_2);
  181. //
  182. // /* configure the tmr1 CH3 pin */
  183. // gpio_init_struct.gpio_pins = PWM_CH_PIN;
  184. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  185. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  186. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  187. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  188. // gpio_init(PWM_CH_GPIO_PORT, &gpio_init_struct);
  189. //
  190. // gpio_pin_mux_config(PWM_CH_GPIO_PORT, GPIO_PINS_SOURCE10, GPIO_MUX_2);
  191. //
  192. // /* configure the tmr1 CH3C pin */
  193. // gpio_init_struct.gpio_pins = PWM_CL_PIN;
  194. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  195. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  196. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  197. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  198. // gpio_init(PWM_CL_GPIO_PORT, &gpio_init_struct);
  199. //
  200. // gpio_pin_mux_config(PWM_CL_GPIO_PORT, GPIO_PINS_SOURCE15, GPIO_MUX_2);
  201. //
  202. // /* configure the tmr1 CH4 pin */
  203. // gpio_init_struct.gpio_pins = GPIO_PINS_11;
  204. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  205. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  206. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  207. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE;
  208. // gpio_init(GPIOA, &gpio_init_struct);
  209. // gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE11, GPIO_MUX_2);
  210. }
  211. /*************************************************************************
  212. Function:
  213. Description:
  214. Call by:
  215. Input Variables:
  216. Output/Return Variables:
  217. Subroutine Call:
  218. Reference:
  219. *************************************************************************/
  220. void hw_voInitDMA(void)
  221. {
  222. // /*=======================================================================
  223. // DMA1 Ch5 for Timer1
  224. // =======================================================================*/
  225. // // DMA_InitTypeDef DMA_InitStructure;
  226. //
  227. //// DMA_DeInit(DMA1_Channel5);
  228. //// DMA_InitStructure.DMA_PeripheralBaseAddr = (ULONG)(&TIM1->DMAR); //澶栬鍦板潃
  229. //// DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
  230. //// DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; //涓嶆墽琛屽璁惧湴鍧�澧為噺鎿嶄綔
  231. //// DMA_InitStructure.DMA_MemoryBaseAddr = (ULONG)hw_uwPWMCmpr;//(pwm_stGenOut.uwNewTIM1COMPR); // 鍐呭瓨鍦板潃
  232. //// DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
  233. //// DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; //鎵ц瀛樺偍鍣ㄥ湴鍧�澧為噺鎿嶄綔
  234. //// DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;//浠庡瓨鍌ㄥ櫒鍒板璁�
  235. //// DMA_InitStructure.DMA_BufferSize = TIM1_DMA_NUM; //6閫氶亾
  236. //// DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; //鎵ц寰幆鎿嶄綔
  237. //// DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; //浼樺厛绾ф渶楂�
  238. //// DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; //
  239. //// DMA_Init(DMA1_Channel5, &DMA_InitStructure);
  240. //// /* Enable DMA1 Channel 5 */
  241. //// //DMA_Cmd(DMA1_Channel5, ENABLE);
  242. //
  243. // wk_dma1_channel5_init();
  244. // wk_dma_channel_config(DMA1_CHANNEL5,(uint32_t)&TMR1->dmadt, (uint32_t)hw_uwPWMCmpr, TIM1_DMA_NUM);
  245. //
  246. // /*=======================================================================
  247. // DMA1 Ch1 for ADC1
  248. // =======================================================================*/
  249. //// DMA_DeInit(DMA1_Channel1);
  250. ////
  251. //// DMA_InitStructure.DMA_PeripheralBaseAddr = (ULONG)(&ADC1->DR);
  252. //// DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
  253. //// DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
  254. //// DMA_InitStructure.DMA_MemoryBaseAddr = (ULONG)(hw_uwADC1);
  255. //// DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
  256. //// DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
  257. //// DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
  258. //// DMA_InitStructure.DMA_BufferSize = ADC1_DMA_NUM;
  259. //// DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
  260. //// DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
  261. //// DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
  262. //// DMA_Init(DMA1_Channel1, &DMA_InitStructure);
  263. //// /* Enable DMA1 Channel1 */
  264. //// DMA_Cmd(DMA1_Channel1, ENABLE);
  265. //wk_dma1_channel1_init();
  266. //wk_dma_channel_config(DMA1_CHANNEL1, (uint32_t)&ADC1->odt, (uint32_t)(hw_uwADC1), ADC1_DMA_NUM);
  267. //dma_channel_enable(DMA1_CHANNEL1, TRUE);
  268. /*=======================================================================
  269. DMA1 Ch3 for UART3 receive
  270. =======================================================================*/
  271. /*=======================================================================
  272. DMA1 Ch2 for UART3 transmission
  273. =======================================================================*/
  274. // DMA_Cmd(DMA1_Channel2, ENABLE);
  275. }
  276. /*************************************************************************
  277. Function:
  278. Description:
  279. Call by:
  280. Input Variables:
  281. Output/Return Variables:
  282. Subroutine Call:
  283. Reference:
  284. *************************************************************************/
  285. void hw_voInitADC(void)
  286. {
  287. // wk_adc1_init();
  288. }
  289. void hw_SetIphaseSample(void)
  290. {
  291. // ADC1->psq_bit.pclen =3-1; //adc_preempt_channel_length_set(ADC1, 3);
  292. //
  293. // ADC1->psq_bit.psn2 = ADC_CHANNEL_0; //閲囨牱閫氶亾1
  294. // ADC1->psq_bit.psn3 = ADC_CHANNEL_1; //閲囨牱閫氶亾2
  295. // ADC1->psq_bit.psn4 = ADC_CHANNEL_3; //閲囨牱閫氶亾3
  296. // adc_preempt_channel_length_set(ADC1, 3);
  297. // adc_preempt_channel_set(ADC1, ADC_CHANNEL_0, 1, ADC_SAMPLETIME_1_5);
  298. // adc_preempt_offset_value_set(ADC1, ADC_PREEMPT_CHANNEL_1, 0x0);
  299. // adc_preempt_channel_set(ADC1, ADC_CHANNEL_1, 2, ADC_SAMPLETIME_1_5);
  300. // adc_preempt_offset_value_set(ADC1, ADC_PREEMPT_CHANNEL_2, 0x0);
  301. // adc_preempt_channel_set(ADC1, ADC_CHANNEL_3, 3, ADC_SAMPLETIME_1_5);
  302. // adc_preempt_offset_value_set(ADC1, ADC_PREEMPT_CHANNEL_3, 0x0);
  303. }
  304. //void hw_SetRdsonSample(adc_channel_select_type adc_channel)
  305. //{
  306. // ADC1->psq_bit.pclen =2-1;//adc_preempt_channel_length_set(ADC1, 2);
  307. //
  308. // ADC1->psq_bit.psn3 = adc_channel; //閲囨牱閫氶亾1
  309. // ADC1->psq_bit.psn4 = ADC_CHANNEL_6; //閲囨牱閫氶亾2 姣嶇嚎鐢垫祦鍊�
  310. //
  311. // adc_preempt_channel_length_set(ADC1, 3);
  312. // adc_preempt_channel_set(ADC1, ADC_CHANNEL_6, 1, ADC_SAMPLETIME_1_5);
  313. // adc_preempt_offset_value_set(ADC1, ADC_PREEMPT_CHANNEL_1, 0x0);
  314. // adc_preempt_channel_set(ADC1, ADC_CHANNEL_0, 2, ADC_SAMPLETIME_1_5);
  315. // adc_preempt_offset_value_set(ADC1, ADC_PREEMPT_CHANNEL_2, 0x0);
  316. // adc_preempt_channel_set(ADC1, ADC_CHANNEL_1, 3, ADC_SAMPLETIME_1_5);
  317. // adc_preempt_offset_value_set(ADC1, ADC_PREEMPT_CHANNEL_3, 0x0);
  318. //}
  319. /*************************************************************************
  320. Function:
  321. Description:OBC
  322. Call by:
  323. Input Variables:
  324. Output/Return Variables:
  325. Subroutine Call:
  326. Reference:
  327. *************************************************************************/
  328. void hw_voInitUART1()
  329. {
  330. // gpio_init_type gpio_init_struct;
  331. //
  332. // /* enable the usart1 and gpio clock */
  333. // crm_periph_clock_enable(CRM_USART1_PERIPH_CLOCK, TRUE);
  334. // crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
  335. //
  336. // gpio_default_para_init(&gpio_init_struct);
  337. //
  338. // /* configure the usart2 tx/rx pin */
  339. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  340. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  341. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  342. // gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
  343. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  344. // gpio_init(GPIOB, &gpio_init_struct);
  345. //
  346. // /* config usart1 iomux */
  347. // gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_0);
  348. // gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_0);
  349. //
  350. //// nvic_irq_enable(USART1_IRQn, 3, 3);
  351. //
  352. // /* configure usart1 param */
  353. // usart_init(USART1, 9600, USART_DATA_8BITS, USART_STOP_1_BIT);
  354. // usart_transmitter_enable(USART1, TRUE);
  355. // usart_receiver_enable(USART1, TRUE);
  356. //// usart_interrupt_enable(USART1, USART_RDBF_INT, TRUE);
  357. //// usart_interrupt_enable(USART1, USART_TDBE_INT, TRUE);
  358. // usart_enable(USART1, TRUE);
  359. }
  360. /*************************************************************************
  361. Function:
  362. Description:BMS
  363. Call by:
  364. Input Variables:
  365. Output/Return Variables:
  366. Subroutine Call:
  367. Reference:
  368. *************************************************************************/
  369. void hw_voInitUART2()
  370. {
  371. // gpio_init_type gpio_init_struct;
  372. //
  373. // /* enable the usart1 and gpio clock */
  374. // crm_periph_clock_enable(CRM_USART2_PERIPH_CLOCK, TRUE);
  375. // crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
  376. //
  377. // gpio_default_para_init(&gpio_init_struct);
  378. //
  379. // gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE14, GPIO_MUX_1);
  380. // gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE15, GPIO_MUX_1);
  381. //
  382. // /* configure the usart2 tx/rx pin */
  383. // gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  384. // gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  385. // gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
  386. // gpio_init_struct.gpio_pins = GPIO_PINS_14 | GPIO_PINS_15;
  387. // gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
  388. // gpio_init(GPIOA, &gpio_init_struct);
  389. //
  390. // /* config usart1 iomux */
  391. //// gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE14, GPIO_MUX_1);
  392. //// gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE15, GPIO_MUX_1);
  393. //
  394. //// nvic_irq_enable(USART2_IRQn, 3, 3);
  395. //
  396. // /* configure usart1 param */
  397. // usart_init(USART2, 9600, USART_DATA_8BITS, USART_STOP_1_BIT);
  398. // usart_transmitter_enable(USART2, TRUE);
  399. // usart_receiver_enable(USART2, TRUE);
  400. //// usart_interrupt_enable(USART2, USART_RDBF_INT, TRUE);
  401. //// usart_interrupt_enable(USART2, USART_TDBE_INT, TRUE);
  402. // usart_enable(USART2, TRUE);
  403. }
  404. /*************************************************************************
  405. Function:
  406. Description:
  407. Call by:
  408. Input Variables:
  409. Output/Return Variables:
  410. Subroutine Call:
  411. Reference:
  412. *************************************************************************/
  413. void hw_voInitTim1(void)
  414. {
  415. // tmr_output_config_type tmr_output_struct;
  416. // tmr_brkdt_config_type tmr_brkdt_struct;
  417. //
  418. //// TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
  419. //// TIM_OCInitTypeDef TIM_OCInitStructure;
  420. //// TIM_BDTRInitTypeDef TIM_BDTRInitStructure;
  421. ////
  422. //// TIM_DeInit(TIM1);
  423. ////
  424. //// /* Time Base configuration */
  425. //// TIM_TimeBaseStructure.TIM_Prescaler = 0; // TIMx->PSC 鍒嗛
  426. //// TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_CenterAligned3; // TIMx->CR1 bit5~6鍚戜笂鍚戜笅鍧囪璁剧疆
  427. //// TIM_TimeBaseStructure.TIM_Period = HW_HPWM_PERIOD; //鑷姩閲嶈杞藉瘎瀛樺櫒 TIMx->ARR
  428. //// TIM_TimeBaseStructure.TIM_ClockDivision = 0; //TIMx->CR1 bit8~9 鏃堕挓鍒嗛鍥犲瓙
  429. //// TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;// TIMx->RCR 閲嶅璁℃暟瀵勫瓨鍣�
  430. //// TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
  431. ////------------
  432. // /* configure counter settings */
  433. // tmr_base_init(TMR1, 2249, 0);
  434. // tmr_cnt_dir_set(TMR1, TMR_COUNT_TWO_WAY_3);
  435. // tmr_clock_source_div_set(TMR1, TMR_CLOCK_DIV1);
  436. // tmr_repetition_counter_set(TMR1, 0);
  437. // // tmr_period_buffer_enable(TMR1, TRUE); //鑷姩閲嶈杞介瑁呰浇鍏佽
  438. //
  439. //
  440. //
  441. ////--------
  442. //
  443. // // TIM1->EGR = 0x0001;//event generation Register,Bit0:UG=1
  444. //
  445. // /* Channel 1, 2,3 Configuration in PWM mode */
  446. //// TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2; //TIMx->CCMR1 bit 4~6 pwm2妯″紡锛�
  447. //// TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Disable;//TIMx->CCER bit0 鍏抽棴锛� OC1绂佹杈撳嚭
  448. //// TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Disable;// TIMx->CCER bit2 TIMx->CCER 鍏抽棴锛� OC1N绂佹杈撳嚭
  449. //// TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;//TIMx->CCER bit1 OC1楂樼數骞虫湁鏁�
  450. //// TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High; //TIMx->CCER bit4 OC1N楂樼數骞虫湁鏁堬紱
  451. //// TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Reset;//TIMx->CR2 bit8 OC1杈撳嚭绌洪棽鐘舵��
  452. //// TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;//TIMx->CR2 bit9 杈撳嚭绌洪棽鐘舵��
  453. ////
  454. //// TIM_OCInitStructure.TIM_Pulse = HW_HHPWM_PERIOD; //TIMx_CCR1,OC1棰勮杞藉��
  455. //// TIM_OC1Init(TIM1, &TIM_OCInitStructure);
  456. ////
  457. //// TIM_OCInitStructure.TIM_Pulse = HW_HHPWM_PERIOD;//TIMx_CCR2,OC2棰勮杞藉��
  458. //// TIM_OC2Init(TIM1, &TIM_OCInitStructure);
  459. ////
  460. //// TIM_OCInitStructure.TIM_Pulse = HW_HHPWM_PERIOD;//TIMx_CCR3,OC3棰勮杞藉��
  461. //// TIM_OC3Init(TIM1, &TIM_OCInitStructure);
  462. ////
  463. //// /* CH4 configuration as ADC trigger signal */
  464. //// if(cp_stFlg.CurrentSampleModelSelect == SINGLERESISITANCE)
  465. //// {
  466. //// TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
  467. //// TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
  468. //// TIM_OCInitStructure.TIM_Pulse = HW_HPWM_PERIOD - 5;
  469. //// TIM_OC4Init(TIM1, &TIM_OCInitStructure);
  470. //// }
  471. //// else if(cp_stFlg.CurrentSampleModelSelect == RDSON)
  472. //// {
  473. //// TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
  474. //// TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
  475. //// TIM_OCInitStructure.TIM_Pulse = 1;
  476. //// TIM_OC4Init(TIM1, &TIM_OCInitStructure);
  477. //// }
  478. //// else if(cp_stFlg.CurrentSampleModelSelect == COMBINATION)
  479. //// {
  480. //// TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
  481. //// TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
  482. //// TIM_OCInitStructure.TIM_Pulse = 200;
  483. //// TIM_OC4Init(TIM1, &TIM_OCInitStructure);
  484. //// }
  485. //// else if(cp_stFlg.CurrentSampleModelSelect == DOUBLERESISTANCE)
  486. //// {
  487. //// TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; //TIMx->CCER bit12 杈撳嚭浣胯兘
  488. //// TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; //TIMx->CCER 楂樻湁鏁�
  489. //// TIM_OCInitStructure.TIM_Pulse = 1; //TIMx_CCR4 CC4 姣旇緝鍊硷紝1锛屽湪娉㈣胺澶勯噰闆嗙浉鐢垫祦
  490. //// TIM_OC4Init(TIM1, &TIM_OCInitStructure);
  491. //// }
  492. //// else
  493. //// {}
  494. // //-----------------------
  495. // /* configure channel 1 output settings */
  496. // tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_B;
  497. // tmr_output_struct.oc_output_state = FALSE;
  498. // tmr_output_struct.occ_output_state = FALSE;
  499. // tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  500. // tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  501. // tmr_output_struct.oc_idle_state = FALSE;
  502. // tmr_output_struct.occ_idle_state = FALSE;
  503. // tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_1, &tmr_output_struct);
  504. // tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_1, HW_HHPWM_PERIOD); //OC1棰勮杞藉��
  505. // tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_1, FALSE);
  506. //
  507. // tmr_output_channel_immediately_set(TMR1, TMR_SELECT_CHANNEL_1, FALSE);
  508. //
  509. // /* configure channel 2 output settings */
  510. // tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_B;
  511. // tmr_output_struct.oc_output_state = FALSE;
  512. // tmr_output_struct.occ_output_state = FALSE;
  513. // tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  514. // tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  515. // tmr_output_struct.oc_idle_state = FALSE;
  516. // tmr_output_struct.occ_idle_state = FALSE;
  517. // tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_2, &tmr_output_struct);
  518. // tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_2, HW_HHPWM_PERIOD);//OC1棰勮杞藉��
  519. // tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_2, FALSE);
  520. //
  521. // tmr_output_channel_immediately_set(TMR1, TMR_SELECT_CHANNEL_2, FALSE);
  522. //
  523. // /* configure channel 3 output settings */
  524. // tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_B;
  525. // tmr_output_struct.oc_output_state = FALSE;
  526. // tmr_output_struct.occ_output_state = FALSE;
  527. // tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  528. // tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  529. // tmr_output_struct.oc_idle_state = FALSE;
  530. // tmr_output_struct.occ_idle_state = FALSE;
  531. // tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_3, &tmr_output_struct);
  532. // tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_3, HW_HHPWM_PERIOD);//OC1棰勮杞藉��
  533. // tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_3, FALSE);
  534. //
  535. // tmr_output_channel_immediately_set(TMR1, TMR_SELECT_CHANNEL_3, FALSE);
  536. //
  537. // /* configure channel 4 output settings */
  538. // tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_B;
  539. // tmr_output_struct.oc_output_state = FALSE;
  540. // tmr_output_struct.occ_output_state = FALSE;
  541. // tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  542. // tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
  543. // tmr_output_struct.oc_idle_state = FALSE;
  544. // tmr_output_struct.occ_idle_state = FALSE;
  545. // tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_4, &tmr_output_struct);
  546. // tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_4, 108);
  547. // tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_4, FALSE); //杈撳嚭姣旇緝1棰勮杞藉け鑳�
  548. //
  549. // tmr_output_channel_immediately_set(TMR1, TMR_SELECT_CHANNEL_4, FALSE);
  550. //
  551. //
  552. // //-------------------------
  553. // //TIMx->BDTR 鍒硅溅鍜屾鍖哄瘎瀛樺櫒
  554. //// TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable; // bit11 杩愯妯″紡涓嬪綋瀹氭椂鍣ㄤ笉宸ヤ綔鏃讹紝涓�鏃CxE=1鎴朇CxNE=1锛岄鍏堝紑鍚疧C/OCN骞惰緭鍑烘棤鏁堢數骞筹紝鐒跺悗
  555. //// //缃甇C/OCN浣胯兘杈撳嚭淇″彿=1銆�
  556. //// TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable; //bit101 绌洪棽妯″紡涓嬪綋瀹氭椂鍣ㄤ笉宸ヤ綔鏃讹紝涓�鏃CxE=1鎴朇CxNE=1锛� OC/OCN棣栧厛杈撳嚭鍏剁┖闂茬數骞筹紝鐒跺悗
  557. //// // OC/OCN浣胯兘杈撳嚭淇″彿=1銆�
  558. //// TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_2; //閿佸畾绾у埆2
  559. //// TIM_BDTRInitStructure.TIM_DeadTime = cp_stControlPara.swIPMDeadTimeNs / 100 * TIM1CLK_KHZ / 1000 / 10;//bot0~7 姝诲尯浜嬮棿1us
  560. //// TIM_BDTRInitStructure.TIM_Break = TIM_Break_Enable; //bit12 寮�鍚埞杞﹁緭鍏�
  561. //// TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_Low;//bit13 鍒硅溅杈撳叆浣庣數骞虫湁鏁�
  562. //// TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;//bit14 鑷姩杈撳嚭浣胯兘 MOE鍙兘琚蒋浠剁疆鈥�1鈥�
  563. //// TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure);
  564. ////--------------------
  565. // /* configure break and dead-time settings */
  566. // tmr_brkdt_struct.brk_enable = TRUE;//TRUE;//FALSE;//TRUE;
  567. // tmr_brkdt_struct.auto_output_enable = FALSE;
  568. //#if(HARDWAREV30==1)
  569. // tmr_brkdt_struct.brk_polarity =TMR_BRK_INPUT_ACTIVE_HIGH;// TMR_BRK_INPUT_ACTIVE_HIGH;
  570. //#else
  571. // tmr_brkdt_struct.brk_polarity = TMR_BRK_INPUT_ACTIVE_HIGH;//TMR_BRK_INPUT_ACTIVE_LOW;// TMR_BRK_INPUT_ACTIVE_HIGH;
  572. //#endif
  573. // tmr_brkdt_struct.fcsoen_state = TRUE;
  574. // tmr_brkdt_struct.fcsodis_state = TRUE;
  575. // tmr_brkdt_struct.wp_level = TMR_WP_LEVEL_2;
  576. // tmr_brkdt_struct.deadtime = 72;
  577. // tmr_brkdt_config(TMR1, &tmr_brkdt_struct);
  578. // //-------------------
  579. //// TIM_OC1PreloadConfig(TIM1, TIM_OCPreload_Disable);// TIMx->CCMR1 bit3 杈撳嚭姣旇緝1棰勮杞戒娇鑳斤紝闅忔椂鍐欏叆TIMx_CCR1瀵勫瓨鍣紝骞朵笖鏂板啓鍏ョ殑鏁板�肩珛鍗宠捣浣滅敤
  580. //// TIM_OC2PreloadConfig(TIM1, TIM_OCPreload_Disable);//TIMx->CCMR1 bit11
  581. //// TIM_OC3PreloadConfig(TIM1, TIM_OCPreload_Disable);//TIMx->CCMR2 bit3
  582. //// TIM_OC4PreloadConfig(TIM1, TIM_OCPreload_Disable); //TIMx->CCMR2 bit113 Disables the TIM1 peripheral Preload register on CCR4
  583. //// TIM_ARRPreloadConfig(TIM1, ENABLE); //TIMx->CR1 bit7 鑷姩閲嶈杞介瑁呰浇鍏佽浣� Enables TIMx peripheral Preload register on ARR
  584. ////
  585. ////
  586. //// TIM_DMAConfig(TIM1, TIM_DMABase_CCR1, TIM_DMABurstLength_3Transfers);// TIMx->DCR bit0~4 bit8~12 杩炵画浼犻��3涓�氶亾锛孌MA鍩哄湴鍧�TIMx_CR1
  587. ////
  588. ////
  589. //// TIM_SelectMasterSlaveMode(TIM1, TIM_MasterSlaveMode_Enable); //TIMx->SMCR bit7 MSM:1; Master Slave Mode
  590. //// TIM_SelectOutputTrigger(TIM1, TIM_TRGOSource_Update); //TIMx->CR2 bit4~6 涓绘ā寮忛�夋嫨锛屾洿鏂颁簨浠惰閫変负瑙﹀彂杈撳叆(TRGO)
  591. ////
  592. //// /*Main Output ENABLE*/
  593. //// TIM_CtrlPWMOutputs(TIM1, ENABLE); //TIMx->BDTR bit15 MOE 涓昏緭鍑轰娇鑳�
  594. // //------------------
  595. // //tmr_counter_enable(TMR1,TRUE);
  596. // tmr_period_buffer_enable(TMR1, TRUE); //鑷姩閲嶈杞介瑁呰浇鍏佽
  597. // TMR1->dmactrl = 0x0200|TMR_C1DT_ADDRESS; ////DMA1浼犺緭娆℃暟3 锛孴MR_C1DT_ADDRESS
  598. //
  599. //
  600. // /* configure primary mode settings */
  601. // tmr_sub_sync_mode_set(TMR1, TRUE); //娆″畾鏃跺櫒鍚屾
  602. // tmr_primary_mode_select(TMR1, TMR_PRIMARY_SEL_OVERFLOW);//涓诲畾鏃跺櫒杈撳嚭淇″彿閫夋嫨:婧㈠嚭浜嬩欢
  603. //
  604. // tmr_output_enable(TMR1,TRUE);//OEN 涓昏緭鍑轰娇鑳�
  605. //----------------
  606. //
  607. // wk_tmr1_init();
  608. }
  609. /*************************************************************************
  610. Function:
  611. Description:
  612. Call by:
  613. Input Variables:
  614. Output/Return Variables:
  615. Subroutine Call:
  616. Reference:
  617. *************************************************************************/
  618. //void hw_voInitTim2(void)
  619. //{
  620. //
  621. // TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
  622. // TIM_ICInitTypeDef TIM_ICInitStructure;
  623. // TIM_DeInit(TIM2);
  624. //
  625. // /* TIM4 capture of sensor of frequency */
  626. // TIM_TimeBaseStructure.TIM_Prescaler = 0;
  627. // TIM_TimeBaseStructure.TIM_ClockDivision = 0;
  628. // TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
  629. //// TIM_TimeBaseStructure.TIM_Period = FTBC_HZ * 4 / FTBS_HZ - 1;
  630. // TIM_TimeBaseStructure.TIM_Period =TIM2CLK_KHZ * 1000 / FTBS_HZ - 1;
  631. // TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
  632. // TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
  633. //
  634. //// /* Slaves (TIM2) Configuration */
  635. //// TIM_SelectSlaveMode(TIM2, TIM_SlaveMode_External1);
  636. //// /* Selects the Input Trigger source */
  637. //// TIM_SelectInputTrigger(TIM2, TIM_TS_ITR0); // IRT0锟斤拷TIM1
  638. //
  639. // TIM_ARRPreloadConfig(TIM2, ENABLE); // Enables TIMx peripheral Preload register on ARR
  640. // //TIM_SelectMasterSlaveMode(TIM2, TIM_MasterSlaveMode_Enable); // MSM:1; Master Slave Mode
  641. //
  642. // TIM_ICInitStructure.TIM_Channel = TIM_Channel_3;
  643. // TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
  644. // TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
  645. // TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
  646. // TIM_ICInitStructure.TIM_ICFilter = 0;
  647. // TIM_ICInit(TIM2, &TIM_ICInitStructure);
  648. //
  649. // TIM_ICInitStructure.TIM_Channel = TIM_Channel_4;
  650. // TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
  651. // TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
  652. // TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
  653. // TIM_ICInitStructure.TIM_ICFilter = 0;
  654. // TIM_ICInit(TIM2, &TIM_ICInitStructure);
  655. //}
  656. /*************************************************************************
  657. Function:
  658. Description:
  659. Call by:
  660. Input Variables:
  661. Output/Return Variables:
  662. Subroutine Call:
  663. Reference:
  664. *************************************************************************/
  665. //void hw_voInitTim3(void)
  666. //{
  667. //
  668. // TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
  669. // TIM_ICInitTypeDef TIM_ICInitStructure;
  670. //
  671. // TIM_DeInit(TIM3);
  672. //
  673. // /* TIM3 capture of sensor of frequency */
  674. // TIM_TimeBaseStructure.TIM_Prescaler = 19; // TIMx_PSC, Counter clock frequency = fCK_PSC/(PSC[15:0]+1)
  675. // TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
  676. // TIM_TimeBaseStructure.TIM_Period = 60000; //[15:0] Maximum count value 65535
  677. // TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
  678. // TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
  679. // TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
  680. //
  681. // /* Hall IC Signal */
  682. // TIM_ICInitStructure.TIM_Channel = TIM_Channel_1;
  683. // TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
  684. // TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
  685. // TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
  686. // TIM_ICInitStructure.TIM_ICFilter = 0x0;
  687. // TIM_ICInit(TIM3, &TIM_ICInitStructure);
  688. //
  689. // TIM_ICInitStructure.TIM_Channel = TIM_Channel_2;
  690. // TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
  691. // TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
  692. // TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
  693. // TIM_ICInitStructure.TIM_ICFilter = 0x0;
  694. // TIM_ICInit(TIM3, &TIM_ICInitStructure);
  695. //
  696. // TIM_ICInitStructure.TIM_Channel = TIM_Channel_3;
  697. // TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
  698. // TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
  699. // TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
  700. // TIM_ICInitStructure.TIM_ICFilter = 0x0;
  701. // TIM_ICInit(TIM3, &TIM_ICInitStructure);
  702. //
  703. // TIM_ARRPreloadConfig(TIM3, ENABLE); // Enables TIMx peripheral Preload register on ARR
  704. //
  705. //}
  706. /*************************************************************************
  707. Function:
  708. Description:
  709. Call by:
  710. Input Variables:
  711. Output/Return Variables:
  712. Subroutine Call:
  713. Reference:
  714. *************************************************************************/
  715. //void hw_voInitTim4(void)
  716. //{
  717. // TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
  718. // TIM_DeInit(TIM4);
  719. //
  720. // TIM_TimeBaseStructure.TIM_Prescaler = 0;
  721. // TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
  722. // TIM_TimeBaseStructure.TIM_Period = APB2CLK_KHZ * 1000 / FPWM_HZ * 2; //HW_PWM_PERIOD * 2;
  723. // TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
  724. // TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
  725. // TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
  726. //
  727. // TIM_ARRPreloadConfig(TIM4, ENABLE); // Enables TIMx peripheral Preload register on ARR
  728. //}
  729. /*************************************************************************
  730. Function:
  731. Description:
  732. Call by:
  733. Input Variables:
  734. Output/Return Variables:
  735. Subroutine Call:
  736. Reference:
  737. *************************************************************************/
  738. /*************************************************************************
  739. Function:
  740. Description:
  741. Call by:
  742. Input Variables:
  743. Output/Return Variables:
  744. Subroutine Call:
  745. Reference:
  746. *************************************************************************/
  747. void hw_voInitSysTick(void)
  748. {
  749. /* Setup systick timer interrupts */
  750. //SysTick_Config(SystemCoreClock / FSYSTICK_HZ);
  751. // systick_interrupt_config(system_core_clock / 8 / 1000);
  752. }
  753. /*************************************************************************
  754. Function:
  755. Description:
  756. Call by:
  757. Input Variables:
  758. Output/Return Variables:
  759. Subroutine Call:
  760. Reference: 浼樺厛绾�
  761. *************************************************************************/
  762. void hw_voInitInt(void)
  763. {
  764. // NVIC_InitTypeDef NVIC_InitStructure;
  765. //
  766. // NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
  767. //
  768. // /* Enable the ADC1,2 Interrupt */
  769. // NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn;
  770. // NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
  771. // NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
  772. // NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  773. // NVIC_Init(&NVIC_InitStructure);
  774. //
  775. // /* Enable the TIM1 Interrupt PWM Interrupt*/
  776. // NVIC_InitStructure.NVIC_IRQChannel = TIM1_UP_IRQn;
  777. // NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
  778. // NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
  779. // NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  780. // NVIC_Init(&NVIC_InitStructure);
  781. //
  782. //
  783. // /* Enable TIM2 Interrupt TIM2 CAP*/
  784. // NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
  785. // NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
  786. // NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
  787. // NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  788. // NVIC_Init(&NVIC_InitStructure);
  789. //
  790. // /* Enable TIM3 Interrupt, TIM3 HALL CAP*/
  791. // NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;
  792. // NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
  793. // NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
  794. // NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  795. // NVIC_Init(&NVIC_InitStructure);
  796. // wk_nvic_config();
  797. }
  798. /*************************************************************************
  799. Function:
  800. Description:
  801. Call by:
  802. Input Variables:
  803. Output/Return Variables:
  804. Subroutine Call:
  805. Reference:涓柇寮�鍚�
  806. *************************************************************************/
  807. void hw_voEnInt(void)
  808. {
  809. // /* ADC group conversion Interrupts enable */
  810. // if(cp_stFlg.CurrentSampleModelSelect== SINGLERESISITANCE)
  811. // {
  812. // ADC_ITConfig(ADC2, ADC_IT_JEOC, ENABLE);
  813. // }
  814. // else if((cp_stFlg.CurrentSampleModelSelect == DOUBLERESISTANCE) || (cp_stFlg.CurrentSampleModelSelect== RDSON))
  815. // {
  816. // ADC_ITConfig(ADC1, ADC_IT_JEOC, ENABLE);
  817. // }
  818. // else if(cp_stFlg.CurrentSampleModelSelect== COMBINATION)
  819. // {
  820. // ADC_ITConfig(ADC1, ADC_IT_JEOC, ENABLE);
  821. // ADC_ITConfig(ADC2, ADC_IT_JEOC, ENABLE);
  822. // }
  823. // else
  824. // {
  825. //
  826. // }
  827. //
  828. // /* TIM1 Interrupts enable */
  829. // TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE);
  830. //// TIM_ITConfig(TIM1, TIM_IT_CC4, ENABLE);
  831. //
  832. // /* TIM2 Interrupts enable */
  833. // TIM_ITConfig(TIM2, TIM_IT_CC3, ENABLE);
  834. // TIM_ITConfig(TIM2, TIM_IT_CC4, ENABLE);
  835. // TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);
  836. //
  837. // /* TIM3 Interrupts enable */
  838. // TIM_ITConfig(TIM3, TIM_IT_Update, ENABLE);
  839. // TIM_ITConfig(TIM3, TIM_IT_CC1, ENABLE);
  840. // TIM_ITConfig(TIM3, TIM_IT_CC2, ENABLE);
  841. // TIM_ITConfig(TIM3, TIM_IT_CC3, ENABLE);
  842. //
  843. // /* DMA full transfer finish interrupt */
  844. // DMA_ITConfig(DMA1_Channel2, DMA_IT_TC, ENABLE);
  845. // DMA_ITConfig(DMA1_Channel3, DMA_IT_TC, ENABLE);
  846. //--------------------
  847. /* add user code begin adc1_init 2 */
  848. //adc_interrupt_enable(ADC1,ADC_CCE_INT,TRUE);
  849. // adc_interrupt_enable(ADC1,ADC_PCCE_INT,TRUE);
  850. //// dma_interrupt_enable(DMA1_CHANNEL1,DMA_FDT_INT,TRUE);
  851. //
  852. // /* add user code begin tmr1_init 2 */
  853. // tmr_interrupt_enable(TMR1,TMR_OVF_INT,TRUE);
  854. // tmr_flag_clear(TMR1,TMR_BRK_FLAG);
  855. // tmr_interrupt_enable(TMR1,TMR_BRK_INT,TRUE);
  856. //
  857. // // (TMR16,TMR_C1_INT,TRUE);
  858. // tmr_flag_clear(TMR16, TMR_C1_INT | TMR_OVF_INT );
  859. // tmr_interrupt_enable(TMR16,TMR_OVF_INT,TRUE);
  860. // tmr_interrupt_enable(TMR16,TMR_C1_INT,TRUE);
  861. //
  862. // // (TMR17,TMR_C1_INT,TRUE);
  863. // tmr_flag_clear(TMR17, TMR_C1_INT | TMR_OVF_INT );
  864. // tmr_interrupt_enable(TMR17,TMR_OVF_INT,TRUE);
  865. // tmr_interrupt_enable(TMR17,TMR_C1_INT,TRUE);
  866. // //------time3
  867. // tmr_flag_clear(TMR3, TMR_C1_INT | TMR_OVF_INT |TMR_C2_INT |TMR_C3_INT);
  868. // tmr_interrupt_enable(TMR3, TMR_C1_INT, TRUE);
  869. // tmr_interrupt_enable(TMR3, TMR_C2_INT, TRUE);
  870. // tmr_interrupt_enable(TMR3, TMR_C3_INT, TRUE);
  871. // tmr_interrupt_enable(TMR3, TMR_OVF_INT, TRUE);
  872. //
  873. // usart_interrupt_enable(USART1, USART_RDBF_INT, TRUE);
  874. // usart_interrupt_enable(USART1, USART_TDBE_INT, TRUE);
  875. //
  876. //#if (SIMULATION == 0)
  877. // usart_interrupt_enable(USART2, USART_RDBF_INT, TRUE);
  878. // usart_interrupt_enable(USART2, USART_TDBE_INT, TRUE);
  879. //#endif
  880. }
  881. /*************************************************************************
  882. Function:
  883. Description:
  884. Call by:
  885. Input Variables:
  886. Output/Return Variables:
  887. Subroutine Call:
  888. Reference:寮�鍚鏁�
  889. *************************************************************************/
  890. void hw_voTimEn(void)
  891. {
  892. // tmr_counter_enable(TMR1, TRUE);
  893. // tmr_counter_enable(TMR3, TRUE);
  894. // tmr_counter_enable(TMR6, TRUE);
  895. // tmr_counter_enable(TMR16, TRUE);
  896. // tmr_counter_enable(TMR17, TRUE);
  897. // /* TIM1 counter enable */
  898. // TIM_Cmd(TIM1, ENABLE);
  899. // /* TIM2 counter enable */
  900. // TIM_Cmd(TIM2, ENABLE);
  901. // /* TIM3 counter enable */
  902. // TIM_Cmd(TIM3, ENABLE);
  903. // /* TIM4 counter enable */
  904. // TIM_Cmd(TIM4, ENABLE);
  905. // DL_TimerA_startCounter(MOTOR_PWM_INST);
  906. }
  907. /*************************************************************************
  908. Function:
  909. Description:
  910. Call by:
  911. Input Variables:
  912. Output/Return Variables:
  913. Subroutine Call:
  914. Reference:pwm鍒濆鍖�
  915. *************************************************************************/
  916. void hw_voPWMInit(void)
  917. {
  918. /* Set 50% duty */
  919. pwm_stGenOut.uwNewTIM1COMPR[0] = HW_HHPWM_PERIOD;
  920. pwm_stGenOut.uwNewTIM1COMPR[1] = HW_HHPWM_PERIOD;
  921. pwm_stGenOut.uwNewTIM1COMPR[2] = HW_HHPWM_PERIOD;
  922. pwm_stGenOut.uwNewTIM1COMPR[3] = HW_HHPWM_PERIOD;
  923. pwm_stGenOut.uwNewTIM1COMPR[4] = HW_HHPWM_PERIOD;
  924. pwm_stGenOut.uwNewTIM1COMPR[5] = HW_HHPWM_PERIOD;
  925. /* PWM off */
  926. hw_voPWMOff();
  927. /* Charge init */
  928. hw_uwChrgCt = 0;
  929. hw_blChrgOvrFlg = FALSE;
  930. }
  931. /*************************************************************************
  932. Function:
  933. Description:
  934. Call by:
  935. Input Variables:
  936. Output/Return Variables:
  937. Subroutine Call:
  938. Reference:寮�椹卞姩
  939. *************************************************************************/
  940. void hw_voPWMOn(void)
  941. {
  942. if (hw_blPWMOnFlg == FALSE)
  943. {
  944. // /* CH1, CH2 set to "PWM mode 2" */
  945. // TMR1->cm1 |= 0x7070;// TIM1->CCMR1 |= 0x7070;
  946. // /* CH3 set to "PWM mode 2" */
  947. // TMR1->cm2 |= 0x7070;// TIM1->CCMR2 |= 0x7070;
  948. // /* CH1, CH2 and CH3 output enable */
  949. // TMR1->cctrl |= 0x5555;// TIM1->CCER |= 0x5555; 楂樻湁鏁�
  950. //// TIM1->CCER |= 0x0FFF;
  951. //
  952. // /* Flag set */
  953. DL_Timer_overrideCCPOut(MOTOR_PWM_INST, DL_TIMER_FORCE_OUT_DISABLED, DL_TIMER_FORCE_CMPL_OUT_DISABLED, DL_TIMER_CC_0_INDEX);
  954. DL_Timer_overrideCCPOut(MOTOR_PWM_INST, DL_TIMER_FORCE_OUT_DISABLED, DL_TIMER_FORCE_CMPL_OUT_DISABLED, DL_TIMER_CC_1_INDEX);
  955. DL_Timer_overrideCCPOut(MOTOR_PWM_INST, DL_TIMER_FORCE_OUT_DISABLED, DL_TIMER_FORCE_CMPL_OUT_DISABLED, DL_TIMER_CC_2_INDEX);
  956. hw_blPWMOnFlg = TRUE;
  957. }
  958. }
  959. /*************************************************************************
  960. Function:
  961. Description:
  962. Call by:
  963. Input Variables:
  964. Output/Return Variables:
  965. Subroutine Call:
  966. Reference:鍏抽┍鍔�
  967. *************************************************************************/
  968. void hw_voPWMOff(void)
  969. {
  970. if (hw_blPWMOnFlg == TRUE)
  971. {
  972. // /* CH1, CH2 set to "Frozen" */
  973. // TMR1->cm1 &= ~0x7070;// TIM1->CCMR1 &= ~0x7070;
  974. // /* CH3 set to "Frozen" */
  975. //// TIM1->CCMR2 &= ~0x7070;
  976. // TMR1->cm2&= ~0x0070; // TIM1->CCMR2 &= ~0x0070; //don't change CC4
  977. // /* CH1, CH2 set to "Force inactive level" */
  978. // TMR1->cm1 |= 0x4040;// TIM1->CCMR1 |= 0x4040;
  979. // /* CH3 set to "Force inactive level" */
  980. //// TIM1->CCMR2 |= 0x4040;
  981. // TMR1->cm2 |= 0x0040; // TIM1->CCMR2 |= 0x0040; //don't change CC4
  982. // /* CH1, CH2 and CH3 complementary output disable */
  983. //// TIM1->CCER &= ~0x4444;
  984. // TMR1->cctrl &= ~0x4444;//TIM1->CCER &= ~0x4444;
  985. //
  986. DL_Timer_overrideCCPOut(MOTOR_PWM_INST, DL_TIMER_FORCE_OUT_LOW, DL_TIMER_FORCE_CMPL_OUT_LOW, DL_TIMER_CC_0_INDEX);
  987. DL_Timer_overrideCCPOut(MOTOR_PWM_INST, DL_TIMER_FORCE_OUT_LOW, DL_TIMER_FORCE_CMPL_OUT_LOW, DL_TIMER_CC_1_INDEX);
  988. DL_Timer_overrideCCPOut(MOTOR_PWM_INST, DL_TIMER_FORCE_OUT_LOW, DL_TIMER_FORCE_CMPL_OUT_LOW, DL_TIMER_CC_2_INDEX);
  989. /* Flag set */
  990. hw_blPWMOnFlg = FALSE;
  991. }
  992. }
  993. /*************************************************************************
  994. Function:
  995. Description:
  996. Call by:
  997. Input Variables:
  998. Output/Return Variables:
  999. Subroutine Call:
  1000. Reference:50%鍗犵┖姣旇嚜妫�
  1001. *************************************************************************/
  1002. void hw_voCharge(void)
  1003. {
  1004. /* Set 50% duty */
  1005. pwm_stGenOut.uwNewTIM1COMPR[0] = HW_HHPWM_PERIOD;
  1006. pwm_stGenOut.uwNewTIM1COMPR[1] = HW_HHPWM_PERIOD;
  1007. pwm_stGenOut.uwNewTIM1COMPR[2] = HW_HHPWM_PERIOD;
  1008. pwm_stGenOut.uwNewTIM1COMPR[3] = HW_HHPWM_PERIOD;
  1009. pwm_stGenOut.uwNewTIM1COMPR[4] = HW_HHPWM_PERIOD;
  1010. pwm_stGenOut.uwNewTIM1COMPR[5] = HW_HHPWM_PERIOD;
  1011. // pwm_stGenOut.uwNewTIM1COMPR[0] = 337;
  1012. // pwm_stGenOut.uwNewTIM1COMPR[1] = HW_HHPWM_PERIOD;
  1013. // pwm_stGenOut.uwNewTIM1COMPR[2] = HW_HHPWM_PERIOD;
  1014. // pwm_stGenOut.uwNewTIM1COMPR[3] = 337;
  1015. // pwm_stGenOut.uwNewTIM1COMPR[4] = HW_HHPWM_PERIOD;
  1016. // pwm_stGenOut.uwNewTIM1COMPR[5] = HW_HHPWM_PERIOD;
  1017. /* PWM on */
  1018. hw_voPWMOn();
  1019. if (++hw_uwChrgCt > cp_stControlPara.swIPMHvicChrgMs)
  1020. {
  1021. hw_uwChrgCt = 0;
  1022. hw_blChrgOvrFlg = TRUE;
  1023. }
  1024. }
  1025. /* Three phase short */
  1026. /*************************************************************************
  1027. Function:
  1028. Description:
  1029. Call by:
  1030. Input Variables:
  1031. Output/Return Variables:
  1032. Subroutine Call:
  1033. Reference:
  1034. *************************************************************************/
  1035. void hw_voThrPhsShrt(void)
  1036. {
  1037. /* Set 0% duty */
  1038. pwm_stGenOut.uwNewTIM1COMPR[0] = HW_HPWM_PERIOD;
  1039. pwm_stGenOut.uwNewTIM1COMPR[1] = HW_HPWM_PERIOD;
  1040. pwm_stGenOut.uwNewTIM1COMPR[2] = HW_HPWM_PERIOD;
  1041. pwm_stGenOut.uwNewTIM1COMPR[3] = HW_HPWM_PERIOD;
  1042. pwm_stGenOut.uwNewTIM1COMPR[4] = HW_HPWM_PERIOD;
  1043. pwm_stGenOut.uwNewTIM1COMPR[5] = HW_HPWM_PERIOD;
  1044. pwm_stGenOut.uwFirstTrigCOMPR = HW_HHHPWM_PERIOD;
  1045. pwm_stGenOut.uwSecondTrigCOMPR = HW_HPWM_PERIOD - HW_HHHPWM_PERIOD;
  1046. /* PWM on */
  1047. hw_voPWMOn();
  1048. }
  1049. /*************************************************************************
  1050. Function
  1051. Description: Initialize UART
  1052. Call by: ;
  1053. Input Variables: N/A
  1054. Output/Return Variables: N/A
  1055. Subroutine Call: ...;
  1056. Reference: N/A鐪嬮棬鐙�
  1057. ****************************************************************/
  1058. void hw_voIWDGInit(UWORD prer, UWORD rlr)
  1059. {
  1060. // RCC_LSICmd(ENABLE);
  1061. // while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) != SET)
  1062. // {}
  1063. // IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
  1064. // IWDG_SetPrescaler(prer);
  1065. // IWDG_SetReload(rlr);
  1066. // IWDG_ReloadCounter();
  1067. // IWDG_Enable();
  1068. }
  1069. /*************************************************************************
  1070. Copyright (c) 2018 Welling Motor Technology(Shanghai) Co. Ltd.
  1071. All rights reserved.
  1072. *************************************************************************/
  1073. #ifdef _HWSETUP_C_
  1074. #undef _HWSETUP_C_
  1075. #endif
  1076. /************************************************************************
  1077. End of this File (EOF)!
  1078. Do not put anything after this part!
  1079. *************************************************************************/