ARM Macro Assembler Page 1 1 00000000 ;******************************************************* *********************** 2 00000000 3 00000000 THUMB 4 00000000 REQUIRE8 5 00000000 PRESERVE8 6 00000000 7 00000000 AREA |.text|, CODE, READONLY, ALIGN= 2 8 00000000 9 00000000 ; Reference to the FailSafe routine to be executed in ca se of non-recoverable 10 00000000 ; failure 11 00000000 IMPORT FailSafePOR 12 00000000 13 00000000 ;; C variables for control flow monitoring 14 00000000 IMPORT CtrlFlowCnt 15 00000000 IMPORT CtrlFlowCntInv 16 00000000 17 00000000 ;******************************************************* ************************ 18 00000000 ; Function Name : STL_StartUpCPUTest 19 00000000 ; Description : Full Cortex-M3 CPU test at start-up 20 00000000 ; Note: when possible, BRANCH are 16-bi t only (depending on 21 00000000 ; relative offset to final BL instructi on) 22 00000000 ; Input : None. 23 00000000 ; Output : Branch directly to a Fail Safe routin e in case of failure 24 00000000 ; Return : CPUTEST_SUCCESS (=1) 25 00000000 ; WARNING : all registers destroyed when exiting this function (including 26 00000000 ; preserved registers R4 to R11) and ex cluding stack point R13) 27 00000000 ;******************************************************* ************************/ 28 00000000 29 00000000 STU_CPURegsAddressing PROC ;64.7us 30 00000000 EXPORT STU_CPURegsAddressing 31 00000000 32 00000000 E92D 1FFF PUSH {R0-R12} 33 00000004 34 00000004 2000 MOVS R0, #0x00 35 00000006 2100 MOVS R1, #0x00 36 00000008 2200 MOVS R2, #0x00 37 0000000A 2300 MOVS R3, #0x00 38 0000000C 2400 MOVS R4, #0x00 39 0000000E 2500 MOVS R5, #0x00 40 00000010 2600 MOVS R6, #0x00 41 00000012 2700 MOVS R7, #0x00 42 00000014 F05F 0800 MOVS R8, #0x00 43 00000018 F05F 0900 MOVS R9, #0x00 44 0000001C F05F 0A00 MOVS R10, #0x00 45 00000020 F05F 0B00 MOVS R11, #0x00 46 00000024 F05F 0C00 MOVS R12, #0x00 47 00000028 48 00000028 2000 MOVS R0, #0x00 ARM Macro Assembler Page 2 49 0000002A 2101 MOVS R1, #0x01 50 0000002C 2202 MOVS R2, #0x02 51 0000002E 2303 MOVS R3, #0x03 52 00000030 2404 MOVS R4, #0x04 53 00000032 2505 MOVS R5, #0x05 54 00000034 2606 MOVS R6, #0x06 55 00000036 2707 MOVS R7, #0x07 56 00000038 F05F 0808 MOVS R8, #0x08 57 0000003C F05F 0909 MOVS R9, #0x09 58 00000040 F05F 0A0A MOVS R10, #0x0A 59 00000044 F05F 0B0B MOVS R11, #0x0B 60 00000048 F05F 0C0C MOVS R12, #0x0C 61 0000004C 62 0000004C 2800 CMP R0, #0x00 63 0000004E D11D BNE __REGS_ADDRESSING_ERR 64 00000050 2901 CMP R1, #0x01 65 00000052 D11B BNE __REGS_ADDRESSING_ERR 66 00000054 2A02 CMP R2, #0x02 67 00000056 D119 BNE __REGS_ADDRESSING_ERR 68 00000058 2B03 CMP R3, #0x03 69 0000005A D117 BNE __REGS_ADDRESSING_ERR 70 0000005C 2C04 CMP R4, #0x04 71 0000005E D115 BNE __REGS_ADDRESSING_ERR 72 00000060 2D05 CMP R5, #0x05 73 00000062 D113 BNE __REGS_ADDRESSING_ERR 74 00000064 2E06 CMP R6, #0x06 75 00000066 D111 BNE __REGS_ADDRESSING_ERR 76 00000068 2F07 CMP R7, #0x07 77 0000006A D10F BNE __REGS_ADDRESSING_ERR 78 0000006C F1B8 0F08 CMP R8, #0x08 79 00000070 D10C BNE __REGS_ADDRESSING_ERR 80 00000072 F1B9 0F09 CMP R9, #0x09 81 00000076 D109 BNE __REGS_ADDRESSING_ERR 82 00000078 F1BA 0F0A CMP R10, #0x0A 83 0000007C D106 BNE __REGS_ADDRESSING_ERR 84 0000007E F1BB 0F0B CMP R11, #0x0B 85 00000082 D103 BNE __REGS_ADDRESSING_ERR 86 00000084 F1BC 0F0C CMP R12, #0x0C 87 00000088 D100 BNE __REGS_ADDRESSING_ERR 88 0000008A 89 0000008A E001 B __REGS_ADDRESSING_RET 90 0000008C 91 0000008C __REGS_ADDRESSING_ERR 92 0000008C F7FF BFFE B FailSafePOR 93 00000090 94 00000090 __REGS_ADDRESSING_RET 95 00000090 E8BD 1FFF POP {R0-R12} 96 00000094 97 00000094 4770 BX LR ; return to the cal ler 98 00000096 ENDP 99 00000096 END Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw ork --depend=.\qd007a_ctl_app\stm32f1xx_stucpuregsaddressing.d -o.\qd007a_ctl_a pp\stm32f1xx_stucpuregsaddressing.o -ID:\SoftDesign\20190311_QD007A_CTL\QD007E_ CTRL_APP\QD007E_CTRL_APP\MDK-ARM\RTE -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\4.4.0\CMSI S\Include -IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\1.1.0\Device\Include --prede fine="__MICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 515" --predefine=" _RTE_ SETA 1" --predefine="STM32F10X_MD SETA 1" --list=stm32f1xx_stucpuregsaddr ARM Macro Assembler Page 3 essing.lst ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddressing.s ARM Macro Assembler Page 1 Alphabetic symbol ordering Relocatable symbols .text 00000000 Symbol: .text Definitions At line 7 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddres sing.s Uses None Comment: .text unused STU_CPURegsAddressing 00000000 Symbol: STU_CPURegsAddressing Definitions At line 29 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s Uses At line 30 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s Comment: STU_CPURegsAddressing used once __REGS_ADDRESSING_ERR 0000008C Symbol: __REGS_ADDRESSING_ERR Definitions At line 91 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s Uses At line 63 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s At line 65 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s At line 67 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s At line 69 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s At line 71 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s At line 73 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s At line 75 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s At line 77 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s At line 79 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s At line 81 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s At line 83 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s At line 85 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s At line 87 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s __REGS_ADDRESSING_RET 00000090 Symbol: __REGS_ADDRESSING_RET Definitions At line 94 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s ARM Macro Assembler Page 2 Alphabetic symbol ordering Relocatable symbols Uses At line 89 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s Comment: __REGS_ADDRESSING_RET used once 4 symbols ARM Macro Assembler Page 1 Alphabetic symbol ordering External symbols CtrlFlowCnt 00000000 Symbol: CtrlFlowCnt Definitions At line 14 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s Uses None Comment: CtrlFlowCnt unused CtrlFlowCntInv 00000000 Symbol: CtrlFlowCntInv Definitions At line 15 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s Uses None Comment: CtrlFlowCntInv unused FailSafePOR 00000000 Symbol: FailSafePOR Definitions At line 11 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s Uses At line 92 in file ..\SelfTestUser\src_specific\stm32f1xx_STUCpuRegsAddre ssing.s Comment: FailSafePOR used once 3 symbols 341 symbols in table