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+/*
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+ * File: LoadObsTheta.c
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+ *
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+ * Code generated for Simulink model 'LoadObsTheta'.
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+ *
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+ * Model version : 8.72
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+ * Simulink Coder version : 9.6 (R2021b) 14-May-2021
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+ * C/C++ source code generated on : Sat Nov 5 15:46:39 2022
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+ *
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+ * Target selection: ert.tlc
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+ * Embedded hardware selection: ARM Compatible->ARM Cortex-M
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+ * Code generation objectives: Unspecified
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+ * Validation result: Not run
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+ */
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+
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+#include "LoadObsTheta.h"
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+#ifndef UCHAR_MAX
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+#include <limits.h>
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+#endif
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+
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+#if ( UCHAR_MAX != (0xFFU) ) || ( SCHAR_MAX != (0x7F) )
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+#error Code was generated for compiler with different sized uchar/char. \
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+Consider adjusting Test hardware word size settings on the \
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+Hardware Implementation pane to match your compiler word sizes as \
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+defined in limits.h of the compiler. Alternatively, you can \
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+select the Test hardware is the same as production hardware option and \
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+select the Enable portable word sizes option on the Code Generation > \
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+Verification pane for ERT based targets, which will disable the \
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+preprocessor word size checks.
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+#endif
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+
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+#if ( USHRT_MAX != (0xFFFFU) ) || ( SHRT_MAX != (0x7FFF) )
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+#error Code was generated for compiler with different sized ushort/short. \
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+Consider adjusting Test hardware word size settings on the \
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+Hardware Implementation pane to match your compiler word sizes as \
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+defined in limits.h of the compiler. Alternatively, you can \
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+select the Test hardware is the same as production hardware option and \
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+select the Enable portable word sizes option on the Code Generation > \
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+Verification pane for ERT based targets, which will disable the \
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+preprocessor word size checks.
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+#endif
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+
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+#if ( UINT_MAX != (0xFFFFFFFFU) ) || ( INT_MAX != (0x7FFFFFFF) )
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+#error Code was generated for compiler with different sized uint/int. \
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+Consider adjusting Test hardware word size settings on the \
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+Hardware Implementation pane to match your compiler word sizes as \
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+defined in limits.h of the compiler. Alternatively, you can \
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+select the Test hardware is the same as production hardware option and \
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+select the Enable portable word sizes option on the Code Generation > \
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+Verification pane for ERT based targets, which will disable the \
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+preprocessor word size checks.
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+#endif
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+
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+#if ( ULONG_MAX != (0xFFFFFFFFU) ) || ( LONG_MAX != (0x7FFFFFFF) )
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+#error Code was generated for compiler with different sized ulong/long. \
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+Consider adjusting Test hardware word size settings on the \
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+Hardware Implementation pane to match your compiler word sizes as \
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+defined in limits.h of the compiler. Alternatively, you can \
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+select the Test hardware is the same as production hardware option and \
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+select the Enable portable word sizes option on the Code Generation > \
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+Verification pane for ERT based targets, which will disable the \
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+preprocessor word size checks.
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+#endif
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+
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+/* Skipping ulong_long/long_long check: insufficient preprocessor integer range. */
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+
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+/* Exported data definition */
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+
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+/* Definition for custom storage class: Struct */
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+LoadObsTheta_stCoef_type LoadObsTheta_stCoef;
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+LoadObsTheta_stCoefIn_type LoadObsTheta_stCoefIn;
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+
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+/* Block states (default storage) */
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+DW_LoadObsTheta_T LoadObsTheta_DW;
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+
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+/* External inputs (root inport signals with default storage) */
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+ExtU_LoadObsTheta_T LoadObsTheta_U;
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+
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+/* External outputs (root outports fed by signals with default storage) */
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+ExtY_LoadObsTheta_T LoadObsTheta_Y;
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+void LoadObsTheta_voCoef(void)
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+{
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+ uint16_T rtb_Divide2;
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+
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+ /* Outputs for Atomic SubSystem: '<Root>/Initialize Function2' */
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+ /* Product: '<S2>/Divide' incorporates:
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+ * DataStoreWrite: '<S2>/Data Store Write'
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+ * Inport: '<Root>/uwFbHz'
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+ * Inport: '<Root>/uwWtcHz'
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+ */
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+ LoadObsTheta_stCoef.uwK1Pu = (uint16_T)(LoadObsTheta_stCoefIn.uwFbHz == 0U ?
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+ MAX_uint32_T : ((uint32_T)LoadObsTheta_stCoefIn.uwWtcHz << 15) /
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+ LoadObsTheta_stCoefIn.uwFbHz);
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+
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+ /* Product: '<S2>/Divide2' incorporates:
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+ * Gain: '<S2>/Gain'
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+ * Inport: '<Root>/uwJb'
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+ * Inport: '<Root>/uwMtJm'
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+ */
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+ rtb_Divide2 = (uint16_T)(LoadObsTheta_stCoefIn.uwJb == 0U ? MAX_uint32_T :
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+ 1000U * LoadObsTheta_stCoefIn.uwMtJm / LoadObsTheta_stCoefIn.uwJb);
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+
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+ /* Product: '<S2>/Product6' incorporates:
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+ * DataStoreWrite: '<S2>/Data Store Write'
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+ * DataStoreWrite: '<S2>/Data Store Write1'
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+ * Product: '<S2>/Divide'
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+ * Product: '<S2>/Product'
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+ */
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+ LoadObsTheta_stCoef.uwK2Pu = (uint16_T)(((uint64_T)(((uint32_T)
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+ LoadObsTheta_stCoef.uwK1Pu * LoadObsTheta_stCoef.uwK1Pu) >> 1) *
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+ rtb_Divide2) >> 19);
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+
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+ /* Product: '<S2>/Divide6' incorporates:
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+ * DataStoreRead: '<S2>/Data Store Read'
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+ * DataStoreWrite: '<S2>/Data Store Write'
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+ * DataStoreWrite: '<S2>/Data Store Write2'
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+ * Inport: '<Root>/uwMCoef'
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+ * Product: '<S2>/Divide'
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+ * Product: '<S2>/Product1'
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+ * Product: '<S2>/Product2'
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+ * Product: '<S2>/Product4'
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+ * Product: '<S2>/Product5'
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+ */
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+ LoadObsTheta_stCoef.uwK3Pu = (uint16_T)(LoadObsTheta_stCoefIn.uwMCoef == 0U ?
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+ MAX_uint32_T : (uint32_T)(uint16_T)(((uint64_T)(uint32_T)(((uint64_T)
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+ (uint32_T)(((uint64_T)(((uint32_T)LoadObsTheta_stCoef.uwK1Pu *
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+ LoadObsTheta_stCoef.uwK1Pu) >> 1) * LoadObsTheta_stCoef.uwK1Pu) >> 14) *
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+ rtb_Divide2) >> 6) * LoadObsTheta_stCoef.uwTctrPu) >> 21) /
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+ LoadObsTheta_stCoefIn.uwMCoef);
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+
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+ /* Product: '<S2>/Divide3' incorporates:
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+ * DataStoreWrite: '<S2>/Data Store Write3'
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+ * Inport: '<Root>/uwFTbcHz'
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+ * Inport: '<Root>/uwFbHz'
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+ */
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+ LoadObsTheta_stCoef.uwCurTs = (uint16_T)(LoadObsTheta_stCoefIn.uwFTbcHz ==
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+ 0U ? MAX_uint32_T : ((uint32_T)LoadObsTheta_stCoefIn.uwFbHz << 10) /
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+ LoadObsTheta_stCoefIn.uwFTbcHz);
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+
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+ /* Product: '<S2>/Divide4' incorporates:
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+ * DataStoreWrite: '<S2>/Data Store Write5'
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+ */
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+ LoadObsTheta_stCoef.uwJmPuInv = (uint16_T)(rtb_Divide2 == 0U ? MAX_uint32_T :
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+ 16384U / rtb_Divide2);
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+
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+ /* Product: '<S2>/Product3' incorporates:
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+ * DataStoreWrite: '<S2>/Data Store Write3'
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+ * DataStoreWrite: '<S2>/Data Store Write7'
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+ * Product: '<S2>/Divide3'
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+ */
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+ LoadObsTheta_stCoef.uwTctrPu = (uint16_T)((LoadObsTheta_stCoef.uwCurTs *
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+ 3217U) >> 7);
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+
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+ /* Product: '<S2>/Divide1' incorporates:
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+ * DataStoreWrite: '<S2>/Data Store Write4'
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+ * Inport: '<Root>/uwFluxWb'
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+ * Inport: '<Root>/uwFluxbWb'
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+ */
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+ LoadObsTheta_stCoef.uwFluxPu = (uint16_T)(LoadObsTheta_stCoefIn.uwFluxbWb ==
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+ 0U ? MAX_uint32_T : ((uint32_T)LoadObsTheta_stCoefIn.uwFluxWb << 12) /
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+ LoadObsTheta_stCoefIn.uwFluxbWb);
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+
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+ /* Product: '<S2>/Divide5' incorporates:
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+ * DataStoreWrite: '<S2>/Data Store Write4'
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+ * DataStoreWrite: '<S2>/Data Store Write6'
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+ * Product: '<S2>/Divide1'
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+ */
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+ LoadObsTheta_stCoef.uwFluxPuInv = (uint16_T)(LoadObsTheta_stCoef.uwFluxPu ==
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+ 0U ? MAX_uint32_T : 16777216U / LoadObsTheta_stCoef.uwFluxPu);
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+
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+ /* End of Outputs for SubSystem: '<Root>/Initialize Function2' */
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+}
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+
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+void LoadObsTheta_voInit(void)
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+{
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+ /* Outputs for Atomic SubSystem: '<Root>/Initialize Function1' */
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+ /* Outport: '<Root>/swSpdFbkPu' incorporates:
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+ * Constant: '<S1>/Constant'
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+ */
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+ LoadObsTheta_Y.swSpdFbkPu = 0;
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+
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+ /* Outport: '<Root>/uwThetaObsPu' incorporates:
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+ * Constant: '<S1>/Constant1'
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+ */
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+ LoadObsTheta_Y.uwThetaObsPu = 0U;
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+
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+ /* Outport: '<Root>/swTLPu' incorporates:
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+ * Constant: '<S1>/Constant2'
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+ */
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+ LoadObsTheta_Y.swTLPu = 0;
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+
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+ /* Outport: '<Root>/swIqCompPu' incorporates:
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+ * Constant: '<S1>/Constant3'
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+ */
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+ LoadObsTheta_Y.swIqCompPu = 0;
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+
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+ /* End of Outputs for SubSystem: '<Root>/Initialize Function1' */
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+}
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+
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+/* Model step function */
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+void LoadObsTheta_step(void)
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+{
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+ int32_T rtb_Sum11;
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+ int16_T rtb_Sum5;
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+
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+ /* Sum: '<S3>/Sum5' incorporates:
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+ * Inport: '<Root>/ThetamPu'
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+ * UnitDelay: '<S3>/Unit Delay4'
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+ */
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+ rtb_Sum5 = (int16_T)(((LoadObsTheta_U.ThetamPu << 13) -
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+ (LoadObsTheta_DW.UnitDelay4_DSTATE >> 1)) >> 13);
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+
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+ /* Switch: '<S3>/Switch2' incorporates:
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+ * Constant: '<S3>/Constant2'
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+ * RelationalOperator: '<S6>/Compare'
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+ * RelationalOperator: '<S7>/Compare'
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+ * Sum: '<S3>/Sum1'
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+ * Sum: '<S3>/Sum5'
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+ * Switch: '<S3>/Switch3'
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+ */
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+ if (rtb_Sum5 >= 16384)
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+ {
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+ rtb_Sum5 = (int16_T)(rtb_Sum5 - 32767);
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+ }
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+ else if (rtb_Sum5 < -16384)
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+ {
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+ /* Switch: '<S3>/Switch2' incorporates:
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+ * Constant: '<S3>/Constant4'
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+ * Sum: '<S3>/Sum4'
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+ * Switch: '<S3>/Switch3'
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+ */
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+ rtb_Sum5 = (int16_T)(rtb_Sum5 + 32767);
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+ }
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+
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+ /* End of Switch: '<S3>/Switch2' */
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+
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+ /* Sum: '<S3>/Sum6' incorporates:
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+ * DataStoreRead: '<S3>/Data Store Read3'
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+ * Product: '<S3>/Product2'
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+ * Switch: '<S3>/Switch2'
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+ * UnitDelay: '<S3>/Unit Delay1'
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+ */
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+ LoadObsTheta_DW.UnitDelay1_DSTATE += LoadObsTheta_stCoef.uwK3Pu * rtb_Sum5;
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+
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+ /* Sum: '<S3>/Sum11' incorporates:
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+ * DataStoreRead: '<S3>/Data Store Read'
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+ * DataStoreRead: '<S3>/Data Store Read1'
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+ * Inport: '<Root>/IqFbkPu'
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+ * Product: '<S3>/Product1'
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+ * Product: '<S3>/Product7'
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+ * Sum: '<S3>/Sum6'
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+ * Sum: '<S3>/Sum9'
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+ * Switch: '<S3>/Switch2'
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+ * UnitDelay: '<S3>/Unit Delay1'
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+ */
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+ rtb_Sum11 = (((int16_T)((LoadObsTheta_U.IqFbkPu *
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+ LoadObsTheta_stCoef.uwFluxPu) >> 14) << 13) +
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+ LoadObsTheta_stCoef.uwK2Pu * rtb_Sum5) +
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+ (LoadObsTheta_DW.UnitDelay1_DSTATE >> 5);
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+
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+ /* Sum: '<S3>/Sum10' incorporates:
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+ * DataStoreRead: '<S3>/Data Store Read4'
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+ * DataStoreRead: '<S3>/Data Store Read6'
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+ * Product: '<S3>/Product4'
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+ * Product: '<S3>/Product5'
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+ * Sum: '<S3>/Sum11'
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+ * UnitDelay: '<S3>/Unit Delay2'
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+ */
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+ LoadObsTheta_DW.UnitDelay2_DSTATE += (int32_T)(((int64_T)
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+ LoadObsTheta_stCoef.uwJmPuInv * rtb_Sum11 * LoadObsTheta_stCoef.uwTctrPu)
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+ >> 22);
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+
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+ /* Saturate: '<S3>/Saturation' incorporates:
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+ * Sum: '<S3>/Sum10'
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+ * UnitDelay: '<S3>/Unit Delay2'
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+ */
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+ if (LoadObsTheta_DW.UnitDelay2_DSTATE > 536870912)
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+ {
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+ /* Outport: '<Root>/swSpdFbkPu' incorporates:
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+ * DataTypeConversion: '<S3>/Data Type Conversion2'
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+ */
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+ LoadObsTheta_Y.swSpdFbkPu = MIN_int16_T;
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+ }
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+ else if (LoadObsTheta_DW.UnitDelay2_DSTATE < -536870912)
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+ {
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+ /* Outport: '<Root>/swSpdFbkPu' incorporates:
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+ * DataTypeConversion: '<S3>/Data Type Conversion2'
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+ */
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+ LoadObsTheta_Y.swSpdFbkPu = MIN_int16_T;
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+ }
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+ else
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+ {
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+ /* Outport: '<Root>/swSpdFbkPu' incorporates:
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+ * DataTypeConversion: '<S3>/Data Type Conversion2'
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+ */
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+ LoadObsTheta_Y.swSpdFbkPu = (int16_T)(LoadObsTheta_DW.UnitDelay2_DSTATE >>
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+ 14);
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+ }
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+
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+ /* End of Saturate: '<S3>/Saturation' */
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+
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+ /* Sum: '<S3>/Sum8' incorporates:
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+ * DataStoreRead: '<S3>/Data Store Read5'
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+ * DataStoreRead: '<S3>/Data Store Read8'
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+ * Product: '<S3>/Product3'
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+ * Product: '<S3>/Product6'
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+ * Sum: '<S3>/Sum10'
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+ * Sum: '<S3>/Sum7'
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+ * Switch: '<S3>/Switch2'
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+ * UnitDelay: '<S3>/Unit Delay2'
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+ * UnitDelay: '<S3>/Unit Delay3'
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+ */
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+ LoadObsTheta_DW.UnitDelay3_DSTATE += (int32_T)(((int64_T)
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+ (((LoadObsTheta_stCoef.uwK1Pu * rtb_Sum5) >> 1) +
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+ LoadObsTheta_DW.UnitDelay2_DSTATE) * LoadObsTheta_stCoef.uwCurTs) >> 10);
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+
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+ /* Switch: '<S3>/Switch' incorporates:
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+ * Constant: '<S3>/Constant1'
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+ * RelationalOperator: '<S4>/Compare'
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+ * RelationalOperator: '<S5>/Compare'
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+ * Sum: '<S3>/Sum2'
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+ * Sum: '<S3>/Sum8'
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+ * Switch: '<S3>/Switch1'
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+ */
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+ if (LoadObsTheta_DW.UnitDelay3_DSTATE >= 536870912)
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+ {
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+ LoadObsTheta_DW.UnitDelay3_DSTATE -= 536870912;
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+ }
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+ else if (LoadObsTheta_DW.UnitDelay3_DSTATE < 0)
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+ {
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+ /* Switch: '<S3>/Switch' incorporates:
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+ * Constant: '<S3>/Constant3'
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+ * Sum: '<S3>/Sum3'
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+ * Switch: '<S3>/Switch1'
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+ * UnitDelay: '<S3>/Unit Delay3'
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+ */
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+ LoadObsTheta_DW.UnitDelay3_DSTATE += 536870912;
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+ }
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+
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+ /* End of Switch: '<S3>/Switch' */
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+
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+ /* Outport: '<Root>/uwThetaObsPu' incorporates:
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+ * DataTypeConversion: '<S3>/Data Type Conversion1'
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+ * Switch: '<S3>/Switch'
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+ * UnitDelay: '<S3>/Unit Delay3'
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+ */
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+ LoadObsTheta_Y.uwThetaObsPu = (uint16_T)(LoadObsTheta_DW.UnitDelay3_DSTATE >>
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+ 14);
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+
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+ /* Outport: '<Root>/swTLPu' incorporates:
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+ * DataTypeConversion: '<S3>/Data Type Conversion3'
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+ * Sum: '<S3>/Sum6'
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+ * UnitDelay: '<S3>/Unit Delay1'
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+ */
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+ LoadObsTheta_Y.swTLPu = (int16_T)(LoadObsTheta_DW.UnitDelay1_DSTATE >> 18);
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+
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+ /* Outport: '<Root>/swIqCompPu' incorporates:
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|
+ * DataStoreRead: '<S3>/Data Store Read2'
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+ * Product: '<S3>/Product8'
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|
+ * Sum: '<S3>/Sum11'
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|
|
+ */
|
|
|
+ LoadObsTheta_Y.swIqCompPu = (int16_T)(((int64_T)
|
|
|
+ LoadObsTheta_stCoef.uwFluxPuInv * rtb_Sum11) >> 23);
|
|
|
+
|
|
|
+ /* Update for UnitDelay: '<S3>/Unit Delay4' incorporates:
|
|
|
+ * Switch: '<S3>/Switch'
|
|
|
+ * UnitDelay: '<S3>/Unit Delay3'
|
|
|
+ */
|
|
|
+ LoadObsTheta_DW.UnitDelay4_DSTATE = LoadObsTheta_DW.UnitDelay3_DSTATE;
|
|
|
+}
|
|
|
+
|
|
|
+/* Model initialize function */
|
|
|
+void LoadObsTheta_initialize(void)
|
|
|
+{
|
|
|
+ /* (no initialization code required) */
|
|
|
+}
|
|
|
+
|
|
|
+/* Model terminate function */
|
|
|
+void LoadObsTheta_terminate(void)
|
|
|
+{
|
|
|
+ /* (no terminate code required) */
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * File trailer for generated code.
|
|
|
+ *
|
|
|
+ * [EOF]
|
|
|
+ */
|