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+//
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+// File: PmsmSimUt.cpp
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+//
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+// Code generated for Simulink model 'PmsmSimUt'.
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+//
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+// Model version : 1.15
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+// Simulink Coder version : 9.4 (R2020b) 29-Jul-2020
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+// C/C++ source code generated on : Fri Jul 28 01:40:47 2023
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+//
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+// Target selection: ert.tlc
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+// Embedded hardware selection: Intel->x86-64 (Windows64)
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+// Code generation objectives: Unspecified
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+// Validation result: Not run
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+//
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+#include "PmsmSimUt.h"
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+#include "PmsmSimUt_private.h"
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+
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+real_T rt_modd_snf(real_T u0, real_T u1)
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+{
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+ real_T q;
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+ real_T y;
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+ boolean_T yEq;
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+ y = u0;
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+ if (u1 == 0.0) {
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+ if (u0 == 0.0) {
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+ y = u1;
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+ }
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+ } else if (rtIsNaN(u0) || rtIsNaN(u1) || rtIsInf(u0)) {
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+ y = (rtNaN);
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+ } else if (u0 == 0.0) {
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+ y = 0.0 / u1;
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+ } else if (rtIsInf(u1)) {
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+ if ((u1 < 0.0) != (u0 < 0.0)) {
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+ y = u1;
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+ }
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+ } else {
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+ y = std::fmod(u0, u1);
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+ yEq = (y == 0.0);
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+ if ((!yEq) && (u1 > std::floor(u1))) {
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+ q = std::abs(u0 / u1);
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+ yEq = !(std::abs(q - std::floor(q + 0.5)) > DBL_EPSILON * q);
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+ }
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+
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+ if (yEq) {
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+ y = u1 * 0.0;
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+ } else {
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+ if ((u0 < 0.0) != (u1 < 0.0)) {
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+ y += u1;
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+ }
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+ }
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+ }
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+
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+ return y;
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+}
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+
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+// Model step function
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+void PmsmSimUtModelClass::step()
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+{
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+ real_T rtb_Gain1_c[3];
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+ real_T rtb_Add1;
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+ real_T rtb_Add2;
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+ real_T rtb_Fcn1;
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+ real_T rtb_Gain;
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+ real_T rtb_Gain1_i;
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+ real_T rtb_Gain2_k;
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+ real_T rtb_Mod;
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+ real_T rtb_Relay2;
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+ real_T rtb_Switch_h;
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+ real_T rtb_Switch_idx_0;
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+ real_T rtb_Switch_idx_1;
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+ real_T rtb_a;
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+ real_T rtb_a_tmp_tmp;
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+ real_T rtb_a_tmp_tmp_0;
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+ real_T rtb_id;
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+ real_T rtb_iq;
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+ int32_T i;
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+ uint8_T rtb_Compare;
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+
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+ // Math: '<S17>/Mod' incorporates:
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+ // Constant: '<S17>/Constant'
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+ // DiscreteIntegrator: '<S17>/Discrete-Time Integrator'
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+
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+ rtb_Mod = rt_modd_snf(PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE,
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+ PmsmSimUt_P.Constant_Value);
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+
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+ // Fcn: '<S16>/id' incorporates:
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+ // Constant: '<S16>/Constant1'
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+ // Constant: '<S16>/Constant2'
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+ // DiscreteIntegrator: '<S16>/Discrete-Time Integrator'
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+
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+ rtb_id = (PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_c -
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+ PmsmSimUt_P.Params.Flux) / PmsmSimUt_P.Params.Ld;
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+
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+ // Fcn: '<S16>/iq' incorporates:
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+ // Constant: '<S16>/Constant3'
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+ // DiscreteIntegrator: '<S16>/Discrete-Time Integrator1'
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+
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+ rtb_iq = PmsmSimUt_DW.DiscreteTimeIntegrator1_DSTATE / PmsmSimUt_P.Params.Lq;
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+
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+ // Outputs for Enabled SubSystem: '<S20>/Subsystem - pi//2 delay' incorporates:
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+ // EnablePort: '<S24>/Enable'
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+
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+ // Outputs for Enabled SubSystem: '<S20>/Subsystem1' incorporates:
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+ // EnablePort: '<S25>/Enable'
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+
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+ // Fcn: '<S28>/Fcn' incorporates:
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+ // Fcn: '<S24>/Fcn'
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+ // Fcn: '<S24>/Fcn1'
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+ // Fcn: '<S25>/Fcn'
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+
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+ rtb_a_tmp_tmp = std::sin(rtb_Mod);
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+ rtb_a_tmp_tmp_0 = std::cos(rtb_Mod);
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+
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+ // End of Outputs for SubSystem: '<S20>/Subsystem1'
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+ // End of Outputs for SubSystem: '<S20>/Subsystem - pi//2 delay'
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+ rtb_a = rtb_a_tmp_tmp_0 * rtb_id - rtb_a_tmp_tmp * rtb_iq;
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+
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+ // Fcn: '<S28>/Fcn1' incorporates:
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+ // Fcn: '<S28>/Fcn'
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+
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+ rtb_Gain1_i = rtb_a_tmp_tmp * rtb_id + rtb_a_tmp_tmp_0 * rtb_iq;
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+
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+ // Gain: '<S29>/K1' incorporates:
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+ // Constant: '<S9>/Constant'
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+
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+ rtb_Gain2_k = PmsmSimUt_P.K1_Gain * PmsmSimUt_P.Constant_Value_e;
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+
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+ // Fcn: '<S29>/a'
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+ rtb_Add2 = rtb_a + rtb_Gain2_k;
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+
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+ // Fcn: '<S29>/b'
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+ rtb_Fcn1 = (-0.5 * rtb_a + 0.8660254037844386 * rtb_Gain1_i) + rtb_Gain2_k;
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+
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+ // Fcn: '<S29>/c'
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+ rtb_a = (-0.5 * rtb_a - 0.8660254037844386 * rtb_Gain1_i) + rtb_Gain2_k;
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+
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+ // Outport: '<Root>/Out' incorporates:
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+ // Gain: '<S29>/K2'
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+
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+ PmsmSimUt_Y.Out.Iabc[0] = PmsmSimUt_P.K2_Gain * rtb_Add2;
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+ PmsmSimUt_Y.Out.Iabc[1] = PmsmSimUt_P.K2_Gain * rtb_Fcn1;
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+ PmsmSimUt_Y.Out.Iabc[2] = PmsmSimUt_P.K2_Gain * rtb_a;
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+
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+ // Switch: '<Root>/Switch2' incorporates:
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+ // Inport: '<Root>/ObsIn'
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+
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+ if (PmsmSimUt_U.ObsIn.Enable > PmsmSimUt_P.Switch2_Threshold) {
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+ rtb_Fcn1 = PmsmSimUt_U.ObsIn.Theta;
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+ } else {
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+ rtb_Fcn1 = rtb_Mod;
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+ }
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+
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+ // End of Switch: '<Root>/Switch2'
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+
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+ // RelationalOperator: '<S10>/Compare' incorporates:
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+ // Constant: '<S10>/Constant'
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+ // Constant: '<S1>/Constant'
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+
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+ rtb_Compare = (PmsmSimUt_P.AlphaBetaZerotodq0_Alignment ==
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+ PmsmSimUt_P.CompareToConstant_const);
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+
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+ // Sum: '<Root>/Add' incorporates:
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+ // Inport: '<Root>/ObsIn'
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+
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+ rtb_Add2 = PmsmSimUt_U.ObsIn.Theta - rtb_Mod;
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+
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+ // Outputs for Enabled SubSystem: '<S1>/Subsystem1' incorporates:
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+ // EnablePort: '<S13>/Enable'
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+
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+ if (rtb_Compare > 0) {
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+ // Fcn: '<S13>/Fcn' incorporates:
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+ // Fcn: '<S13>/Fcn1'
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+
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+ rtb_Gain1_i = std::sin(rtb_Add2);
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+ rtb_Add1 = std::cos(rtb_Add2);
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+
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+ // Fcn: '<S13>/Fcn'
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+ PmsmSimUt_B.Fcn_g = rtb_id * rtb_Add1 + rtb_iq * rtb_Gain1_i;
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+
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+ // Fcn: '<S13>/Fcn1'
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+ PmsmSimUt_B.Fcn1_e = -rtb_id * rtb_Gain1_i + rtb_iq * rtb_Add1;
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+ }
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+
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+ // End of Outputs for SubSystem: '<S1>/Subsystem1'
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+
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+ // Outputs for Enabled SubSystem: '<S1>/Subsystem - pi//2 delay' incorporates:
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+ // EnablePort: '<S12>/Enable'
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+
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+ // RelationalOperator: '<S11>/Compare' incorporates:
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+ // Constant: '<S11>/Constant'
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+ // Constant: '<S1>/Constant'
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+
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+ if (PmsmSimUt_P.AlphaBetaZerotodq0_Alignment ==
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+ PmsmSimUt_P.CompareToConstant1_const) {
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+ // Fcn: '<S12>/Fcn'
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+ PmsmSimUt_B.Fcn_b = rtb_id * std::sin(rtb_Add2) - rtb_iq * std::cos(rtb_Add2);
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+
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+ // Fcn: '<S12>/Fcn1'
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+ PmsmSimUt_B.Fcn1_n = rtb_id * std::cos(rtb_Add2) + rtb_iq * std::sin
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+ (rtb_Add2);
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+ }
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+
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+ // End of RelationalOperator: '<S11>/Compare'
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+ // End of Outputs for SubSystem: '<S1>/Subsystem - pi//2 delay'
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+
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+ // Switch: '<S1>/Switch'
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+ if (rtb_Compare != 0) {
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+ rtb_Switch_idx_0 = PmsmSimUt_B.Fcn_g;
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+ rtb_Switch_idx_1 = PmsmSimUt_B.Fcn1_e;
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+ } else {
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+ rtb_Switch_idx_0 = PmsmSimUt_B.Fcn_b;
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+ rtb_Switch_idx_1 = PmsmSimUt_B.Fcn1_n;
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+ }
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+
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+ // End of Switch: '<S1>/Switch'
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+
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+ // Switch: '<Root>/Switch5' incorporates:
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+ // Inport: '<Root>/ObsIn'
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+
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+ if (PmsmSimUt_U.ObsIn.Enable > PmsmSimUt_P.Switch5_Threshold) {
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+ rtb_Add2 = rtb_Switch_idx_1;
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+ } else {
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+ rtb_Add2 = rtb_iq;
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+ }
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+
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+ // End of Switch: '<Root>/Switch5'
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+
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+ // Gain: '<S16>/Gain' incorporates:
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+ // DiscreteIntegrator: '<S16>/Discrete-Time Integrator'
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+ // DiscreteIntegrator: '<S16>/Discrete-Time Integrator1'
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+ // Fcn: '<S16>/Te//p=(3//2)*(Flux_d*iq-Flux_q*id)'
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+
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+ rtb_Gain = (PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_c * rtb_iq -
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+ PmsmSimUt_DW.DiscreteTimeIntegrator1_DSTATE * rtb_id) * 1.5 *
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+ PmsmSimUt_P.Params.Pn;
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+
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+ // Outputs for Enabled SubSystem: '<S17>/Subsystem' incorporates:
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+ // EnablePort: '<S18>/Enable'
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+
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+ // Constant: '<Root>/Constant2'
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+ if (PmsmSimUt_P.Params.SpdCtrl > 0.0) {
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+ // DiscreteIntegrator: '<S18>/Discrete-Time Integrator1'
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+ PmsmSimUt_B.DiscreteTimeIntegrator1 =
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+ PmsmSimUt_DW.DiscreteTimeIntegrator1_DSTAT_d;
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+
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+ // Update for DiscreteIntegrator: '<S18>/Discrete-Time Integrator1' incorporates:
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+ // Constant: '<S18>/Constant1'
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+ // Gain: '<S18>/Gain'
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+ // Gain: '<S18>/Gain1'
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+ // Inport: '<Root>/CtrlIn'
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+ // Product: '<S18>/Divide'
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+ // Sum: '<S18>/Sum'
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+
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+ PmsmSimUt_DW.DiscreteTimeIntegrator1_DSTAT_d += ((rtb_Gain -
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+ PmsmSimUt_P.Params.B * PmsmSimUt_B.DiscreteTimeIntegrator1) -
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+ PmsmSimUt_U.CtrlIn.Tm) / PmsmSimUt_P.Params.Jm * PmsmSimUt_P.Params.Ts *
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+ PmsmSimUt_P.DiscreteTimeIntegrator1_gainval;
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+ }
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+
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+ // End of Outputs for SubSystem: '<S17>/Subsystem'
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+
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+ // Switch: '<S17>/Switch' incorporates:
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+ // Constant: '<Root>/Constant2'
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+ // Constant: '<Root>/Constant4'
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+ // Gain: '<S17>/Gain3'
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+
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+ if (PmsmSimUt_P.Params.SpdCtrl > PmsmSimUt_P.Switch_Threshold) {
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+ rtb_Gain2_k = PmsmSimUt_B.DiscreteTimeIntegrator1;
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+ } else {
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+ rtb_Gain2_k = PmsmSimUt_P.Gain3_Gain * PmsmSimUt_P.Params.SpdRpm;
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+ }
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+
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+ // End of Switch: '<S17>/Switch'
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+
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+ // Gain: '<S17>/Gain1'
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+ rtb_Gain1_i = PmsmSimUt_P.Params.Pn * rtb_Gain2_k;
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+
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+ // Switch: '<Root>/Switch3' incorporates:
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+ // Inport: '<Root>/ObsIn'
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+
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+ if (PmsmSimUt_U.ObsIn.Enable > PmsmSimUt_P.Switch3_Threshold) {
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+ rtb_a = PmsmSimUt_U.ObsIn.We;
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+ } else {
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+ rtb_a = rtb_Gain1_i;
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+ }
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+
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+ // End of Switch: '<Root>/Switch3'
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+
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+ // Switch: '<Root>/Switch4' incorporates:
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+ // Inport: '<Root>/ObsIn'
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+
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+ if (PmsmSimUt_U.ObsIn.Enable > PmsmSimUt_P.Switch4_Threshold) {
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+ rtb_Add1 = rtb_Switch_idx_0;
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+ } else {
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+ rtb_Add1 = rtb_id;
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+ }
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+
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+ // End of Switch: '<Root>/Switch4'
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+
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+ // ManualSwitch: '<Root>/Manual Switch1' incorporates:
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+ // Constant: '<Root>/Constant5'
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+ // Constant: '<Root>/Constant6'
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+
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+ if (PmsmSimUt_P.ManualSwitch1_CurrentSetting == 1) {
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+ rtb_Switch_idx_0 = PmsmSimUt_P.Constant5_Value;
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+ } else {
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+ rtb_Switch_idx_0 = PmsmSimUt_P.Constant6_Value;
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+ }
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+
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+ // End of ManualSwitch: '<Root>/Manual Switch1'
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+
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+ // Product: '<S5>/Product' incorporates:
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+ // Fcn: '<S5>/Fcn'
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+
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+ rtb_Switch_idx_1 = (8.1e-5 * rtb_Add1 + 0.0789) * rtb_a * rtb_Switch_idx_0;
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+
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+ // Sum: '<Root>/Add1' incorporates:
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+ // Inport: '<Root>/CtrlIn'
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+
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+ rtb_Add1 = PmsmSimUt_U.CtrlIn.IdCmd - rtb_Add1;
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+
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+ // Switch: '<Root>/Switch1' incorporates:
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+ // Fcn: '<S5>/Fcn1'
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+ // Inport: '<Root>/ICtrlIn'
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+ // Product: '<S5>/Product'
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+ // Sum: '<Root>/Sum1'
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+
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+ if (PmsmSimUt_U.ICtrlIn.Enable > PmsmSimUt_P.Switch1_Threshold) {
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+ rtb_Switch_idx_0 = PmsmSimUt_U.ICtrlIn.UdCtrl;
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+ } else {
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+ // Sum: '<S15>/Sum6' incorporates:
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+ // DiscreteIntegrator: '<S15>/Discrete-Time Integrator'
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+ // Gain: '<S15>/Kp4'
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+
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+ rtb_Relay2 = PmsmSimUt_P.Params.CKpd * rtb_Add1 +
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+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_j;
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+
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+ // Saturate: '<S15>/Saturation2'
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+ if (rtb_Relay2 > PmsmSimUt_P.Saturation2_UpperSat_o) {
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+ rtb_Relay2 = PmsmSimUt_P.Saturation2_UpperSat_o;
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+ } else {
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+ if (rtb_Relay2 < PmsmSimUt_P.Saturation2_LowerSat_o) {
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+ rtb_Relay2 = PmsmSimUt_P.Saturation2_LowerSat_o;
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+ }
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+ }
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+
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+ // End of Saturate: '<S15>/Saturation2'
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+ rtb_Switch_idx_0 = -rtb_a * 8.1e-5 * rtb_Add2 * rtb_Switch_idx_0 +
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+ rtb_Relay2;
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+ }
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+
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+ // End of Switch: '<Root>/Switch1'
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+
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+ // Outputs for Enabled SubSystem: '<Root>/Subsystem' incorporates:
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+ // EnablePort: '<S4>/Enable'
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|
+
|
|
|
+ // Logic: '<Root>/AND' incorporates:
|
|
|
+ // Constant: '<Root>/Constant1'
|
|
|
+ // Constant: '<Root>/Constant3'
|
|
|
+ // Logic: '<Root>/NOT'
|
|
|
+
|
|
|
+ if ((!(PmsmSimUt_P.Params.CustomSpdCtrl != 0.0)) &&
|
|
|
+ (PmsmSimUt_P.Params.SpdCtrl != 0.0)) {
|
|
|
+ PmsmSimUt_DW.Subsystem_MODE = true;
|
|
|
+
|
|
|
+ // Saturate: '<Root>/Saturation2' incorporates:
|
|
|
+ // Memory: '<S6>/Memory'
|
|
|
+
|
|
|
+ if (PmsmSimUt_DW.Memory_PreviousInput > PmsmSimUt_P.Saturation2_UpperSat_p)
|
|
|
+ {
|
|
|
+ rtb_Switch_h = PmsmSimUt_P.Saturation2_UpperSat_p;
|
|
|
+ } else if (PmsmSimUt_DW.Memory_PreviousInput <
|
|
|
+ PmsmSimUt_P.Saturation2_LowerSat_f) {
|
|
|
+ rtb_Switch_h = PmsmSimUt_P.Saturation2_LowerSat_f;
|
|
|
+ } else {
|
|
|
+ rtb_Switch_h = PmsmSimUt_DW.Memory_PreviousInput;
|
|
|
+ }
|
|
|
+
|
|
|
+ // End of Saturate: '<Root>/Saturation2'
|
|
|
+
|
|
|
+ // Sum: '<S4>/Add4' incorporates:
|
|
|
+ // Gain: '<Root>/Gain1'
|
|
|
+
|
|
|
+ rtb_Relay2 = rtb_Switch_h - 9.5492965855137211 / PmsmSimUt_P.Params.Pn *
|
|
|
+ rtb_a;
|
|
|
+
|
|
|
+ // DiscreteIntegrator: '<S19>/Discrete-Time Integrator'
|
|
|
+ PmsmSimUt_B.DiscreteTimeIntegrator =
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_n;
|
|
|
+
|
|
|
+ // Sum: '<S19>/Sum6' incorporates:
|
|
|
+ // Gain: '<S19>/Kp4'
|
|
|
+
|
|
|
+ PmsmSimUt_B.Iq_ref = PmsmSimUt_P.Params.SKp * rtb_Relay2 +
|
|
|
+ PmsmSimUt_B.DiscreteTimeIntegrator;
|
|
|
+
|
|
|
+ // Saturate: '<S19>/Saturation2'
|
|
|
+ if (PmsmSimUt_B.Iq_ref > PmsmSimUt_P.Saturation2_UpperSat) {
|
|
|
+ // Sum: '<S19>/Sum6' incorporates:
|
|
|
+ // Saturate: '<S19>/Saturation2'
|
|
|
+
|
|
|
+ PmsmSimUt_B.Iq_ref = PmsmSimUt_P.Saturation2_UpperSat;
|
|
|
+ } else {
|
|
|
+ if (PmsmSimUt_B.Iq_ref < PmsmSimUt_P.Saturation2_LowerSat) {
|
|
|
+ // Sum: '<S19>/Sum6' incorporates:
|
|
|
+ // Saturate: '<S19>/Saturation2'
|
|
|
+
|
|
|
+ PmsmSimUt_B.Iq_ref = PmsmSimUt_P.Saturation2_LowerSat;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ // End of Saturate: '<S19>/Saturation2'
|
|
|
+
|
|
|
+ // Update for DiscreteIntegrator: '<S19>/Discrete-Time Integrator' incorporates:
|
|
|
+ // Gain: '<S19>/Gain'
|
|
|
+ // Gain: '<S19>/Kp5'
|
|
|
+
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_n += PmsmSimUt_P.Params.SKi *
|
|
|
+ rtb_Relay2 * PmsmSimUt_P.Params.Ts *
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator_gainval;
|
|
|
+ if (PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_n >=
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator_UpperSat) {
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_n =
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator_UpperSat;
|
|
|
+ } else {
|
|
|
+ if (PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_n <=
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator_LowerSat) {
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_n =
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator_LowerSat;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ // End of Update for DiscreteIntegrator: '<S19>/Discrete-Time Integrator'
|
|
|
+
|
|
|
+ // Switch: '<Root>/Switch'
|
|
|
+ rtb_Switch_h = PmsmSimUt_B.Iq_ref;
|
|
|
+ } else {
|
|
|
+ if (PmsmSimUt_DW.Subsystem_MODE) {
|
|
|
+ // Disable for DiscreteIntegrator: '<S19>/Discrete-Time Integrator'
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_n =
|
|
|
+ PmsmSimUt_B.DiscreteTimeIntegrator;
|
|
|
+ PmsmSimUt_DW.Subsystem_MODE = false;
|
|
|
+ }
|
|
|
+
|
|
|
+ // Switch: '<Root>/Switch' incorporates:
|
|
|
+ // Inport: '<Root>/CtrlIn'
|
|
|
+
|
|
|
+ rtb_Switch_h = PmsmSimUt_U.CtrlIn.IqCmd;
|
|
|
+ }
|
|
|
+
|
|
|
+ // End of Logic: '<Root>/AND'
|
|
|
+ // End of Outputs for SubSystem: '<Root>/Subsystem'
|
|
|
+
|
|
|
+ // Sum: '<Root>/Add2'
|
|
|
+ rtb_Add2 = rtb_Switch_h - rtb_Add2;
|
|
|
+
|
|
|
+ // Switch: '<Root>/Switch6' incorporates:
|
|
|
+ // Inport: '<Root>/ICtrlIn'
|
|
|
+ // Sum: '<Root>/Sum'
|
|
|
+
|
|
|
+ if (PmsmSimUt_U.ICtrlIn.Enable > PmsmSimUt_P.Switch6_Threshold) {
|
|
|
+ rtb_a = PmsmSimUt_U.ICtrlIn.UqCtrl;
|
|
|
+ } else {
|
|
|
+ // Sum: '<S14>/Sum6' incorporates:
|
|
|
+ // DiscreteIntegrator: '<S14>/Discrete-Time Integrator'
|
|
|
+ // Gain: '<S14>/Kp4'
|
|
|
+
|
|
|
+ rtb_Relay2 = PmsmSimUt_P.Params.CKpq * rtb_Add2 +
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_g;
|
|
|
+
|
|
|
+ // Saturate: '<S14>/Saturation2'
|
|
|
+ if (rtb_Relay2 > PmsmSimUt_P.Saturation2_UpperSat_b) {
|
|
|
+ rtb_Relay2 = PmsmSimUt_P.Saturation2_UpperSat_b;
|
|
|
+ } else {
|
|
|
+ if (rtb_Relay2 < PmsmSimUt_P.Saturation2_LowerSat_j) {
|
|
|
+ rtb_Relay2 = PmsmSimUt_P.Saturation2_LowerSat_j;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ // End of Saturate: '<S14>/Saturation2'
|
|
|
+ rtb_a = rtb_Switch_idx_1 + rtb_Relay2;
|
|
|
+ }
|
|
|
+
|
|
|
+ // End of Switch: '<Root>/Switch6'
|
|
|
+
|
|
|
+ // Fcn: '<S26>/Fcn' incorporates:
|
|
|
+ // Fcn: '<S26>/Fcn1'
|
|
|
+
|
|
|
+ rtb_Relay2 = std::sin(rtb_Fcn1);
|
|
|
+ rtb_Fcn1 = std::cos(rtb_Fcn1);
|
|
|
+ rtb_Switch_idx_1 = rtb_Fcn1 * rtb_Switch_idx_0 - rtb_Relay2 * rtb_a;
|
|
|
+
|
|
|
+ // Fcn: '<S26>/Fcn1'
|
|
|
+ rtb_Fcn1 = rtb_Relay2 * rtb_Switch_idx_0 + rtb_Fcn1 * rtb_a;
|
|
|
+
|
|
|
+ // Gain: '<S27>/K1' incorporates:
|
|
|
+ // Constant: '<S8>/Constant'
|
|
|
+
|
|
|
+ rtb_Switch_idx_0 = PmsmSimUt_P.K1_Gain_j * PmsmSimUt_P.Constant_Value_p;
|
|
|
+
|
|
|
+ // Fcn: '<S27>/a'
|
|
|
+ rtb_a = rtb_Switch_idx_1 + rtb_Switch_idx_0;
|
|
|
+
|
|
|
+ // Fcn: '<S27>/b'
|
|
|
+ rtb_Relay2 = (-0.5 * rtb_Switch_idx_1 + 0.8660254037844386 * rtb_Fcn1) +
|
|
|
+ rtb_Switch_idx_0;
|
|
|
+
|
|
|
+ // Fcn: '<S27>/c'
|
|
|
+ rtb_Switch_idx_1 = (-0.5 * rtb_Switch_idx_1 - 0.8660254037844386 * rtb_Fcn1) +
|
|
|
+ rtb_Switch_idx_0;
|
|
|
+
|
|
|
+ // Gain: '<S27>/K2'
|
|
|
+ rtb_Fcn1 = PmsmSimUt_P.K2_Gain_b * rtb_a;
|
|
|
+ rtb_a = PmsmSimUt_P.K2_Gain_b * rtb_Relay2;
|
|
|
+ rtb_Relay2 = PmsmSimUt_P.K2_Gain_b * rtb_Switch_idx_1;
|
|
|
+ for (i = 0; i < 3; i++) {
|
|
|
+ // Gain: '<S21>/Gain1' incorporates:
|
|
|
+ // Gain: '<S21>/Gain3'
|
|
|
+
|
|
|
+ rtb_Gain1_c[i] = PmsmSimUt_P.Gain1_Gain * (PmsmSimUt_P.Gain3_Gain_j[i + 6] *
|
|
|
+ rtb_Relay2 + (PmsmSimUt_P.Gain3_Gain_j[i + 3] * rtb_a +
|
|
|
+ PmsmSimUt_P.Gain3_Gain_j[i] * rtb_Fcn1));
|
|
|
+ }
|
|
|
+
|
|
|
+ // RelationalOperator: '<S22>/Compare' incorporates:
|
|
|
+ // Constant: '<S20>/Constant'
|
|
|
+ // Constant: '<S22>/Constant'
|
|
|
+
|
|
|
+ rtb_Compare = (PmsmSimUt_P.AlphaBetaZerotodq0_Alignment_e ==
|
|
|
+ PmsmSimUt_P.CompareToConstant_const_a);
|
|
|
+
|
|
|
+ // Outputs for Enabled SubSystem: '<S20>/Subsystem1' incorporates:
|
|
|
+ // EnablePort: '<S25>/Enable'
|
|
|
+
|
|
|
+ if (rtb_Compare > 0) {
|
|
|
+ // Fcn: '<S25>/Fcn'
|
|
|
+ PmsmSimUt_B.Fcn = rtb_Gain1_c[0] * rtb_a_tmp_tmp_0 + rtb_Gain1_c[1] *
|
|
|
+ rtb_a_tmp_tmp;
|
|
|
+
|
|
|
+ // Fcn: '<S25>/Fcn1'
|
|
|
+ PmsmSimUt_B.Fcn1 = -rtb_Gain1_c[0] * rtb_a_tmp_tmp + rtb_Gain1_c[1] *
|
|
|
+ rtb_a_tmp_tmp_0;
|
|
|
+ }
|
|
|
+
|
|
|
+ // End of Outputs for SubSystem: '<S20>/Subsystem1'
|
|
|
+
|
|
|
+ // Outputs for Enabled SubSystem: '<S20>/Subsystem - pi//2 delay' incorporates:
|
|
|
+ // EnablePort: '<S24>/Enable'
|
|
|
+
|
|
|
+ // RelationalOperator: '<S23>/Compare' incorporates:
|
|
|
+ // Constant: '<S20>/Constant'
|
|
|
+ // Constant: '<S23>/Constant'
|
|
|
+
|
|
|
+ if (PmsmSimUt_P.AlphaBetaZerotodq0_Alignment_e ==
|
|
|
+ PmsmSimUt_P.CompareToConstant1_const_o) {
|
|
|
+ // Fcn: '<S24>/Fcn'
|
|
|
+ PmsmSimUt_B.Fcn_a = rtb_Gain1_c[0] * rtb_a_tmp_tmp - rtb_Gain1_c[1] *
|
|
|
+ rtb_a_tmp_tmp_0;
|
|
|
+
|
|
|
+ // Fcn: '<S24>/Fcn1'
|
|
|
+ PmsmSimUt_B.Fcn1_p = rtb_Gain1_c[0] * rtb_a_tmp_tmp_0 + rtb_Gain1_c[1] *
|
|
|
+ rtb_a_tmp_tmp;
|
|
|
+ }
|
|
|
+
|
|
|
+ // End of RelationalOperator: '<S23>/Compare'
|
|
|
+ // End of Outputs for SubSystem: '<S20>/Subsystem - pi//2 delay'
|
|
|
+
|
|
|
+ // Switch: '<S20>/Switch'
|
|
|
+ if (rtb_Compare != 0) {
|
|
|
+ rtb_Switch_idx_0 = PmsmSimUt_B.Fcn;
|
|
|
+ rtb_Switch_idx_1 = PmsmSimUt_B.Fcn1;
|
|
|
+ } else {
|
|
|
+ rtb_Switch_idx_0 = PmsmSimUt_B.Fcn_a;
|
|
|
+ rtb_Switch_idx_1 = PmsmSimUt_B.Fcn1_p;
|
|
|
+ }
|
|
|
+
|
|
|
+ // End of Switch: '<S20>/Switch'
|
|
|
+
|
|
|
+ // Outport: '<Root>/Out' incorporates:
|
|
|
+ // BusCreator: '<Root>/Bus Creator'
|
|
|
+ // DiscreteIntegrator: '<S16>/Discrete-Time Integrator'
|
|
|
+ // DiscreteIntegrator: '<S16>/Discrete-Time Integrator1'
|
|
|
+ // Gain: '<S17>/Gain2'
|
|
|
+ // Inport: '<Root>/CtrlIn'
|
|
|
+ // SignalConversion generated from: '<Root>/Bus Creator'
|
|
|
+
|
|
|
+ PmsmSimUt_Y.Out.WmRpm = PmsmSimUt_P.Gain2_Gain * rtb_Gain2_k;
|
|
|
+ PmsmSimUt_Y.Out.Uabc[0] = rtb_Fcn1;
|
|
|
+ PmsmSimUt_Y.Out.Uabc[1] = rtb_a;
|
|
|
+ PmsmSimUt_Y.Out.Uabc[2] = rtb_Relay2;
|
|
|
+ PmsmSimUt_Y.Out.Idq[0] = rtb_id;
|
|
|
+ PmsmSimUt_Y.Out.Idq[1] = rtb_iq;
|
|
|
+ PmsmSimUt_Y.Out.Te = rtb_Gain;
|
|
|
+ PmsmSimUt_Y.Out.Theta = rtb_Mod;
|
|
|
+ PmsmSimUt_Y.Out.We = rtb_Gain1_i;
|
|
|
+ PmsmSimUt_Y.Out.FluxDq[0] = PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_c;
|
|
|
+ PmsmSimUt_Y.Out.FluxDq[1] = PmsmSimUt_DW.DiscreteTimeIntegrator1_DSTATE;
|
|
|
+ PmsmSimUt_Y.Out.IdRef = PmsmSimUt_U.CtrlIn.IdCmd;
|
|
|
+ PmsmSimUt_Y.Out.IqRef = rtb_Switch_h;
|
|
|
+
|
|
|
+ // Gain: '<S16>/Gain2' incorporates:
|
|
|
+ // Constant: '<S16>/Constant'
|
|
|
+ // DiscreteIntegrator: '<S16>/Discrete-Time Integrator'
|
|
|
+ // Fcn: '<S16>/d(Flux_q)//dt'
|
|
|
+
|
|
|
+ rtb_Mod = ((rtb_Switch_idx_1 - PmsmSimUt_P.Params.R * rtb_iq) - rtb_Gain1_i *
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_c) *
|
|
|
+ PmsmSimUt_P.Params.Ts;
|
|
|
+
|
|
|
+ // Sum: '<S6>/Sum' incorporates:
|
|
|
+ // Inport: '<Root>/CtrlIn'
|
|
|
+ // Memory: '<S6>/Memory'
|
|
|
+
|
|
|
+ rtb_Relay2 = PmsmSimUt_U.CtrlIn.WmRpm - PmsmSimUt_DW.Memory_PreviousInput;
|
|
|
+
|
|
|
+ // DeadZone: '<S6>/Dead Zone'
|
|
|
+ if (rtb_Relay2 > PmsmSimUt_P.DeadZone_End) {
|
|
|
+ rtb_Relay2 -= PmsmSimUt_P.DeadZone_End;
|
|
|
+ } else if (rtb_Relay2 >= PmsmSimUt_P.DeadZone_Start) {
|
|
|
+ rtb_Relay2 = 0.0;
|
|
|
+ } else {
|
|
|
+ rtb_Relay2 -= PmsmSimUt_P.DeadZone_Start;
|
|
|
+ }
|
|
|
+
|
|
|
+ // End of DeadZone: '<S6>/Dead Zone'
|
|
|
+
|
|
|
+ // Relay: '<S6>/Relay1'
|
|
|
+ PmsmSimUt_DW.Relay1_Mode = ((rtb_Relay2 >= PmsmSimUt_P.Relay1_OnVal) ||
|
|
|
+ ((!(rtb_Relay2 <= PmsmSimUt_P.Relay1_OffVal)) && PmsmSimUt_DW.Relay1_Mode));
|
|
|
+
|
|
|
+ // Relay: '<S6>/Relay2'
|
|
|
+ PmsmSimUt_DW.Relay2_Mode = ((rtb_Relay2 >= PmsmSimUt_P.Relay2_OnVal) ||
|
|
|
+ ((!(rtb_Relay2 <= PmsmSimUt_P.Relay2_OffVal)) && PmsmSimUt_DW.Relay2_Mode));
|
|
|
+
|
|
|
+ // Update for DiscreteIntegrator: '<S17>/Discrete-Time Integrator' incorporates:
|
|
|
+ // Gain: '<S17>/Gain'
|
|
|
+
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE += PmsmSimUt_P.Params.Ts *
|
|
|
+ rtb_Gain1_i * PmsmSimUt_P.DiscreteTimeIntegrator_gainva_p;
|
|
|
+
|
|
|
+ // Update for DiscreteIntegrator: '<S16>/Discrete-Time Integrator' incorporates:
|
|
|
+ // Constant: '<S16>/Constant'
|
|
|
+ // DiscreteIntegrator: '<S16>/Discrete-Time Integrator1'
|
|
|
+ // Fcn: '<S16>/d(Flux_d)//dt'
|
|
|
+ // Gain: '<S16>/Gain1'
|
|
|
+
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_c += ((rtb_Switch_idx_0 -
|
|
|
+ PmsmSimUt_P.Params.R * rtb_id) + rtb_Gain1_i *
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator1_DSTATE) * PmsmSimUt_P.Params.Ts *
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator_gainv_pq;
|
|
|
+
|
|
|
+ // Update for DiscreteIntegrator: '<S16>/Discrete-Time Integrator1'
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator1_DSTATE +=
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator1_gainv_b * rtb_Mod;
|
|
|
+
|
|
|
+ // Update for DiscreteIntegrator: '<S15>/Discrete-Time Integrator' incorporates:
|
|
|
+ // Gain: '<S15>/Gain'
|
|
|
+ // Gain: '<S15>/Kp5'
|
|
|
+
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_j += PmsmSimUt_P.Params.CKid *
|
|
|
+ rtb_Add1 * PmsmSimUt_P.Params.Ts *
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator_gainva_b;
|
|
|
+ if (PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_j >=
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator_UpperS_b) {
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_j =
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator_UpperS_b;
|
|
|
+ } else {
|
|
|
+ if (PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_j <=
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator_LowerS_l) {
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_j =
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator_LowerS_l;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ // End of Update for DiscreteIntegrator: '<S15>/Discrete-Time Integrator'
|
|
|
+
|
|
|
+ // Relay: '<S6>/Relay1'
|
|
|
+ if (PmsmSimUt_DW.Relay1_Mode) {
|
|
|
+ rtb_Switch_h = PmsmSimUt_P.Relay1_YOn;
|
|
|
+ } else {
|
|
|
+ rtb_Switch_h = PmsmSimUt_P.Relay1_YOff;
|
|
|
+ }
|
|
|
+
|
|
|
+ // Relay: '<S6>/Relay2'
|
|
|
+ if (PmsmSimUt_DW.Relay2_Mode) {
|
|
|
+ rtb_id = PmsmSimUt_P.Relay2_YOn;
|
|
|
+ } else {
|
|
|
+ rtb_id = PmsmSimUt_P.Relay2_YOff;
|
|
|
+ }
|
|
|
+
|
|
|
+ // Update for Memory: '<S6>/Memory' incorporates:
|
|
|
+ // Gain: '<S6>/Gain'
|
|
|
+ // Sum: '<S6>/Add'
|
|
|
+ // Sum: '<S6>/Sum1'
|
|
|
+
|
|
|
+ PmsmSimUt_DW.Memory_PreviousInput += (rtb_Switch_h + rtb_id) *
|
|
|
+ PmsmSimUt_P.Params.Ts;
|
|
|
+
|
|
|
+ // Update for DiscreteIntegrator: '<S14>/Discrete-Time Integrator' incorporates:
|
|
|
+ // Gain: '<S14>/Gain'
|
|
|
+ // Gain: '<S14>/Kp5'
|
|
|
+
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_g += PmsmSimUt_P.Params.CKiq *
|
|
|
+ rtb_Add2 * PmsmSimUt_P.Params.Ts *
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator_gainva_c;
|
|
|
+ if (PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_g >=
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator_UpperS_k) {
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_g =
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator_UpperS_k;
|
|
|
+ } else {
|
|
|
+ if (PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_g <=
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator_LowerS_a) {
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_g =
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator_LowerS_a;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ // End of Update for DiscreteIntegrator: '<S14>/Discrete-Time Integrator'
|
|
|
+}
|
|
|
+
|
|
|
+// Model initialize function
|
|
|
+void PmsmSimUtModelClass::initialize()
|
|
|
+{
|
|
|
+ // Registration code
|
|
|
+
|
|
|
+ // initialize non-finites
|
|
|
+ rt_InitInfAndNaN(sizeof(real_T));
|
|
|
+
|
|
|
+ // InitializeConditions for DiscreteIntegrator: '<S17>/Discrete-Time Integrator'
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE =
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator_IC;
|
|
|
+
|
|
|
+ // InitializeConditions for DiscreteIntegrator: '<S16>/Discrete-Time Integrator'
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_c = PmsmSimUt_P.Params.Flux;
|
|
|
+
|
|
|
+ // InitializeConditions for DiscreteIntegrator: '<S16>/Discrete-Time Integrator1'
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator1_DSTATE =
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator1_IC_a;
|
|
|
+
|
|
|
+ // InitializeConditions for DiscreteIntegrator: '<S15>/Discrete-Time Integrator'
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_j = PmsmSimUt_P.Subsystem1_Init;
|
|
|
+
|
|
|
+ // InitializeConditions for Memory: '<S6>/Memory'
|
|
|
+ PmsmSimUt_DW.Memory_PreviousInput = PmsmSimUt_P.Memory_InitialCondition;
|
|
|
+
|
|
|
+ // InitializeConditions for DiscreteIntegrator: '<S14>/Discrete-Time Integrator'
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_g = PmsmSimUt_P.Subsystem_Init_c;
|
|
|
+
|
|
|
+ // SystemInitialize for Enabled SubSystem: '<S1>/Subsystem1'
|
|
|
+ // SystemInitialize for Fcn: '<S13>/Fcn' incorporates:
|
|
|
+ // Outport: '<S13>/dq'
|
|
|
+
|
|
|
+ PmsmSimUt_B.Fcn_g = PmsmSimUt_P.dq_Y0_e[0];
|
|
|
+
|
|
|
+ // SystemInitialize for Fcn: '<S13>/Fcn1' incorporates:
|
|
|
+ // Outport: '<S13>/dq'
|
|
|
+
|
|
|
+ PmsmSimUt_B.Fcn1_e = PmsmSimUt_P.dq_Y0_e[1];
|
|
|
+
|
|
|
+ // End of SystemInitialize for SubSystem: '<S1>/Subsystem1'
|
|
|
+
|
|
|
+ // SystemInitialize for Enabled SubSystem: '<S1>/Subsystem - pi//2 delay'
|
|
|
+ // SystemInitialize for Fcn: '<S12>/Fcn' incorporates:
|
|
|
+ // Outport: '<S12>/dq'
|
|
|
+
|
|
|
+ PmsmSimUt_B.Fcn_b = PmsmSimUt_P.dq_Y0[0];
|
|
|
+
|
|
|
+ // SystemInitialize for Fcn: '<S12>/Fcn1' incorporates:
|
|
|
+ // Outport: '<S12>/dq'
|
|
|
+
|
|
|
+ PmsmSimUt_B.Fcn1_n = PmsmSimUt_P.dq_Y0[1];
|
|
|
+
|
|
|
+ // End of SystemInitialize for SubSystem: '<S1>/Subsystem - pi//2 delay'
|
|
|
+
|
|
|
+ // SystemInitialize for Enabled SubSystem: '<S17>/Subsystem'
|
|
|
+ // InitializeConditions for DiscreteIntegrator: '<S18>/Discrete-Time Integrator1'
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator1_DSTAT_d =
|
|
|
+ PmsmSimUt_P.DiscreteTimeIntegrator1_IC;
|
|
|
+
|
|
|
+ // SystemInitialize for DiscreteIntegrator: '<S18>/Discrete-Time Integrator1' incorporates:
|
|
|
+ // Outport: '<S18>/Wm'
|
|
|
+
|
|
|
+ PmsmSimUt_B.DiscreteTimeIntegrator1 = PmsmSimUt_P.Wm_Y0;
|
|
|
+
|
|
|
+ // End of SystemInitialize for SubSystem: '<S17>/Subsystem'
|
|
|
+
|
|
|
+ // SystemInitialize for Enabled SubSystem: '<Root>/Subsystem'
|
|
|
+ // InitializeConditions for DiscreteIntegrator: '<S19>/Discrete-Time Integrator'
|
|
|
+ PmsmSimUt_DW.DiscreteTimeIntegrator_DSTATE_n = PmsmSimUt_P.Subsystem_Init;
|
|
|
+
|
|
|
+ // SystemInitialize for Sum: '<S19>/Sum6' incorporates:
|
|
|
+ // Outport: '<S4>/Iq_ref'
|
|
|
+ // Saturate: '<S19>/Saturation2'
|
|
|
+
|
|
|
+ PmsmSimUt_B.Iq_ref = PmsmSimUt_P.Iq_ref_Y0;
|
|
|
+
|
|
|
+ // End of SystemInitialize for SubSystem: '<Root>/Subsystem'
|
|
|
+
|
|
|
+ // SystemInitialize for Enabled SubSystem: '<S20>/Subsystem1'
|
|
|
+ // SystemInitialize for Fcn: '<S25>/Fcn' incorporates:
|
|
|
+ // Outport: '<S25>/dq'
|
|
|
+
|
|
|
+ PmsmSimUt_B.Fcn = PmsmSimUt_P.dq_Y0_f[0];
|
|
|
+
|
|
|
+ // SystemInitialize for Fcn: '<S25>/Fcn1' incorporates:
|
|
|
+ // Outport: '<S25>/dq'
|
|
|
+
|
|
|
+ PmsmSimUt_B.Fcn1 = PmsmSimUt_P.dq_Y0_f[1];
|
|
|
+
|
|
|
+ // End of SystemInitialize for SubSystem: '<S20>/Subsystem1'
|
|
|
+
|
|
|
+ // SystemInitialize for Enabled SubSystem: '<S20>/Subsystem - pi//2 delay'
|
|
|
+ // SystemInitialize for Fcn: '<S24>/Fcn' incorporates:
|
|
|
+ // Outport: '<S24>/dq'
|
|
|
+
|
|
|
+ PmsmSimUt_B.Fcn_a = PmsmSimUt_P.dq_Y0_l[0];
|
|
|
+
|
|
|
+ // SystemInitialize for Fcn: '<S24>/Fcn1' incorporates:
|
|
|
+ // Outport: '<S24>/dq'
|
|
|
+
|
|
|
+ PmsmSimUt_B.Fcn1_p = PmsmSimUt_P.dq_Y0_l[1];
|
|
|
+
|
|
|
+ // End of SystemInitialize for SubSystem: '<S20>/Subsystem - pi//2 delay'
|
|
|
+}
|
|
|
+
|
|
|
+// Model terminate function
|
|
|
+void PmsmSimUtModelClass::terminate()
|
|
|
+{
|
|
|
+ // (no terminate code required)
|
|
|
+}
|
|
|
+
|
|
|
+// Constructor
|
|
|
+PmsmSimUtModelClass::PmsmSimUtModelClass() :
|
|
|
+ PmsmSimUt_U(),
|
|
|
+ PmsmSimUt_Y(),
|
|
|
+ PmsmSimUt_B(),
|
|
|
+ PmsmSimUt_DW(),
|
|
|
+ PmsmSimUt_M()
|
|
|
+{
|
|
|
+ // Currently there is no constructor body generated.
|
|
|
+}
|
|
|
+
|
|
|
+// Destructor
|
|
|
+PmsmSimUtModelClass::~PmsmSimUtModelClass()
|
|
|
+{
|
|
|
+ // Currently there is no destructor body generated.
|
|
|
+}
|
|
|
+
|
|
|
+// Real-Time Model get method
|
|
|
+PmsmSimUtModelClass::RT_MODEL_PmsmSimUt_T * PmsmSimUtModelClass::getRTM()
|
|
|
+{
|
|
|
+ return (&PmsmSimUt_M);
|
|
|
+}
|
|
|
+
|
|
|
+//
|
|
|
+// File trailer for generated code.
|
|
|
+//
|
|
|
+// [EOF]
|
|
|
+//
|