api_rt_pwm.c 17 KB

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  1. #include "api_rt_pwm.h"
  2. #include "api_rt_dbg.h"
  3. #include "api_rt_timer.h"
  4. #include "board_config.h"
  5. #include "gd32f30x.h"
  6. #include <stdint.h>
  7. #include "api_rt_adc.h"
  8. #include "classB.h"
  9. #include "profiler.h"
  10. ApiRtPwm_Handle Pwms[1];
  11. /* ========================================================================== */
  12. /* ============================ Api RT Functions ============================ */
  13. /* ========================================================================== */
  14. void iRtPwm_Init()
  15. {
  16. Pwms[0].PwmBase = TIMER0;
  17. for (int i = 0; i < 6; i++)
  18. {
  19. Pwms[0].CompareValues[i] = HW_INIT_HHPWM_PERIOD;
  20. Pwms[0].ActiveCompareValues[i] = HW_INIT_HHPWM_PERIOD;
  21. }
  22. Pwms[0].CountZeroISR.Enable = 0;
  23. Pwms[0].CountZeroISR.Action = 0;
  24. Pwms[0].CountMaxISR.Enable = 0;
  25. Pwms[0].CountMaxISR.Action = 0;
  26. Pwms[0].BreakISR.Enable = 0;
  27. Pwms[0].BreakISR.Action = 0;
  28. Pwms[0].OutputEnable = 0;
  29. for (int i = 0; i < 4; i++)
  30. {
  31. Pwms[0].ChannelISR[i].Enable = 0;
  32. Pwms[0].ChannelISR[i].Action = 0;
  33. // Pwms[0].ChannelOutputEnable[i] = 0;
  34. }
  35. #if API_FUNCTION_PWM_SYNC_MULTI_SAMPLING
  36. Pwms[0].SyncSamplingEnable = 1;
  37. Pwms[0].SyncSamplingUpTickCount = 1;
  38. Pwms[0].SyncSamplingUpTick[0] = HW_INIT_HHPWM_PERIOD;
  39. Pwms[0].SyncSamplingDownTickCount = 1;
  40. Pwms[0].SyncSamplingDownTick[0] = HW_SAMPLE_BEFORE_UPDATE_CNTS;
  41. #endif
  42. }
  43. void iRtPwm_CountZeroIsr(uint8_t devIndex)
  44. {
  45. if (Pwms[devIndex].CountZeroISR.Enable)
  46. {
  47. if (Pwms[devIndex].CountZeroISR.Action != 0)
  48. {
  49. Pwms[devIndex].CountZeroISR.Action();
  50. }
  51. }
  52. }
  53. void iRtPwm_CountMaxIsr(uint8_t devIndex)
  54. {
  55. if (Pwms[devIndex].CountMaxISR.Enable)
  56. {
  57. if (Pwms[devIndex].CountMaxISR.Action != 0)
  58. {
  59. Pwms[devIndex].CountMaxISR.Action();
  60. }
  61. }
  62. }
  63. void iRtPwm_UpdateIsr(uint8_t devIndex)
  64. {
  65. uint32_t base = Pwms[devIndex].PwmBase;
  66. uint32_t ulOvTimeCnt = 0;
  67. if(TIMER_INTF(base) & TIMER_INT_FLAG_UP)
  68. {
  69. if((TIMER_CTL0(base) & TIMER_CTL0_DIR) == 0) // When Counting Up
  70. {
  71. PROFILER_START(1);
  72. /* TBC Up interrupt */
  73. iRtPwm_CountZeroIsr(devIndex);
  74. PROFILER_END(1);
  75. }
  76. else
  77. {
  78. PROFILER_START(2);
  79. /* Reset Timer6 counts*/
  80. iTimer_Reset(HW_TBC_HALF_UPDATE_TIMER);
  81. /* TBC Down interrupt */
  82. iRtPwm_CountMaxIsr(devIndex);
  83. /* Timing management, refer to the Software design description for details */
  84. while ((iTimer_GetCount(HW_TBC_HALF_UPDATE_TIMER) < HW_INIT_PWM_PERIOD) && (ulOvTimeCnt < 10000))
  85. {
  86. ulOvTimeCnt++;
  87. };
  88. /* ADC0 trigger set */
  89. iPwm_SetCompareValueImmediate(0,3,Pwms[0].SyncSamplingUpTick[1]);
  90. /* ADC Enable*/
  91. iAdc_Enable(0);
  92. /* Software trigger for regular sampling*/
  93. iAdc_Convert(0);
  94. /* Compara value load */
  95. iRtPwm_ActivateCompareValues(0);
  96. timer_dma_enable(base,TIMER_DMA_UPD);
  97. dma_channel_enable(DMA0,DMA_CH4);
  98. PROFILER_END(2);
  99. }
  100. }
  101. /* Timer0 update interrupt flag clear */
  102. TIMER_INTF(base) = ~(uint32_t)TIMER_INT_FLAG_UP;
  103. }
  104. void iRtPwm_SyncSamplingAdcIsr(uint8_t devIndex)
  105. {
  106. if (ADC_STAT(ADC0) & ADC_INT_FLAG_EOIC)
  107. {
  108. Adcs[1].Results[HW_ADC_IA_CH] = ADC_IDATA0(ADC0);
  109. Adcs[1].Results[HW_ADC_IB_CH] = ADC_IDATA1(ADC0);
  110. Adcs[1].Results[HW_ADC_IC_CH] = ADC_IDATA2(ADC0);
  111. /* ADC0 disable */
  112. ADC_CTL1(ADC0) &= ~((uint32_t)ADC_CTL1_ADCON);
  113. /* ADC1 trigger set */
  114. iPwm_SetCompareValueImmediate(0,3,Pwms[0].SyncSamplingUpTick[0]);
  115. /* ADC1 enable */
  116. ADC_CTL1(ADC1) |= (uint32_t)ADC_CTL1_ADCON;
  117. /* ADC0 interrupt flag clear */
  118. ADC_STAT(ADC0) &= ~((uint32_t)ADC_INT_FLAG_EOIC);
  119. }
  120. else if (ADC_STAT(ADC1) & ADC_INT_FLAG_EOIC)
  121. {
  122. if (Pwms[0].SyncSamplingUpTick[0] != HW_INIT_HHHPWM_PERIOD)
  123. {
  124. Adcs[2].Results[HW_ADC_IDC_CH] = ADC_IDATA0(ADC1);
  125. }
  126. /* ADC1 disable */
  127. ADC_CTL1(ADC1) &= ~((uint32_t)ADC_CTL1_ADCON);
  128. /* ADC1 interrupt flag clear */
  129. ADC_STAT(ADC1) &= ~((uint32_t)ADC_INT_FLAG_EOIC);
  130. }
  131. else
  132. {
  133. //do noting
  134. }
  135. }
  136. void iRtPwm_ActivateCompareValues(uint8_t devIndex)
  137. {
  138. ASSERT_LESS(devIndex, 1);
  139. for (int i = 0; i < 6; i++)
  140. {
  141. Pwms[devIndex].ActiveCompareValues[i] = Pwms[devIndex].CompareValues[i];
  142. }
  143. }
  144. /* ========================================================================== */
  145. /* ============================== API Functions ============================= */
  146. /* ========================================================================== */
  147. uint32_t iPwm_GetClock(uint8_t devIndex)
  148. {
  149. return HW_TIM_CLOCK_HZ;
  150. }
  151. void iPwm_EnableCount(uint8_t devIndex)
  152. {
  153. uint32_t base = Pwms[devIndex].PwmBase;
  154. TIMER_CTL0(base) |= (uint32_t)BIT(0);
  155. }
  156. void iPwm_DisableCount(uint8_t devIndex)
  157. {
  158. uint32_t base = Pwms[devIndex].PwmBase;
  159. TIMER_CTL0(base) &= ~(uint32_t)BIT(0);
  160. }
  161. uint32_t iPwm_GetCountMax(uint8_t devIndex)
  162. {
  163. uint32_t base = Pwms[devIndex].PwmBase;
  164. uint32_t count_value = 0U;
  165. count_value = TIMER_CAR(base);
  166. return count_value;
  167. }
  168. void iPwm_SetCountMax(uint8_t devIndex, uint32_t countMax)
  169. {
  170. uint32_t base = Pwms[devIndex].PwmBase;
  171. TIMER_CAR(base)= countMax;
  172. }
  173. uint32_t iPwm_GetCount(uint8_t devIndex)
  174. {
  175. uint32_t base = Pwms[devIndex].PwmBase;
  176. uint32_t count_value = 0U;
  177. count_value = TIMER_CNT(base);
  178. return count_value;
  179. }
  180. void iPwm_SetCount(uint8_t devIndex, uint32_t count)
  181. {
  182. uint32_t base = Pwms[devIndex].PwmBase;
  183. TIMER_CNT(base)= count;
  184. }
  185. ApiPwm_CountMode iPwm_GetCountMode(uint8_t devIndex)
  186. {
  187. uint32_t base = Pwms[devIndex].PwmBase;
  188. ApiPwm_CountMode mode = ApiPwm_CountUp;
  189. if ((TIMER_CTL0(base) & (uint16_t)0x0060) == (uint16_t)0x0000)
  190. {
  191. if ((TIMER_CTL0(base) & (uint16_t)0x0010) != 0)
  192. {
  193. mode = ApiPwm_CountUp;
  194. }
  195. #if API_FUNCTION_PWM_COUNTDOWN == SUPPORT
  196. else
  197. {
  198. mode = ApiPwm_CountDown;
  199. }
  200. #endif
  201. }
  202. else
  203. {
  204. mode = ApiPwm_CountUpDown;
  205. }
  206. return mode;
  207. }
  208. void iPwm_SetCountMode(uint8_t devIndex, ApiPwm_CountMode mode)
  209. {
  210. uint32_t base = Pwms[devIndex].PwmBase;
  211. switch (mode)
  212. {
  213. case ApiPwm_CountUp:
  214. TIMER_CTL0(base) &= ~((uint16_t)0x0060);
  215. TIMER_CTL0(base) &= ~(uint16_t)0x0010;
  216. break;
  217. #if FUNCTION_PWM_COUNTDOWN == SUPPORT
  218. case ApiPwm_CountDown:
  219. TIMER_CTL0(base) &= ~((uint16_t)0x0060);
  220. TIMER_CTL0(base) |= (uint16_t)0x0010;
  221. break;
  222. #endif
  223. case ApiPwm_CountUpDown:
  224. TIMER_CTL0(base) |= ((uint16_t)0x0060);
  225. break;
  226. default:
  227. break;
  228. }
  229. }
  230. ApiPwm_CompareMode iPwm_GetCompareMode(uint8_t devIndex, uint8_t channelIndex)
  231. {
  232. uint32_t base = Pwms[devIndex].PwmBase;
  233. uint8_t conf = 0;
  234. switch (channelIndex)
  235. {
  236. case 0:
  237. conf = TIMER_CHCTL0(base) & (uint32_t)0x000000F0UL;
  238. break;
  239. case 1:
  240. conf = (TIMER_CHCTL0(base) & (uint32_t)0x0000F000UL) >> 16;
  241. break;
  242. case 2:
  243. conf = TIMER_CHCTL1(base) & (uint32_t)0x000000F0UL;
  244. break;
  245. case 3:
  246. conf = (TIMER_CHCTL1(base) & (uint32_t)0x0000F000UL) >> 16;
  247. break;
  248. default:
  249. break;
  250. }
  251. ApiPwm_CompareMode mode = ApiPwm_NoAction;
  252. switch (conf >> 4)
  253. {
  254. case 0x00:
  255. mode = ApiPwm_NoAction;
  256. break;
  257. case 0x01:
  258. mode = ApiPwm_UpMatchSet;
  259. #if FUNCTION_PWM_COUNTDOWN
  260. if (iPwm_GetCountMode(devIndex) == Pwm_CountDown)
  261. mode = ApiPwm_DownMatchSet;
  262. #endif
  263. break;
  264. case 0x02:
  265. mode = ApiPwm_UpMatchClear;
  266. #if FUNCTION_PWM_COUNTDOWN
  267. if (iPwm_GetCountMode(devIndex) == Pwm_CountDown)
  268. mode = ApiPwm_DownMatchClear;
  269. #endif
  270. break;
  271. case 0x03:
  272. mode = ApiPwm_UpMatchToggle;
  273. #if FUNCTION_PWM_COUNTDOWN
  274. if (iPwm_GetCountMode(devIndex) == Pwm_CountDown)
  275. mode = ApiPwm_DownMatchToggle;
  276. #endif
  277. break;
  278. case 0x04:
  279. mode = ApiPwm_ForceClear;
  280. break;
  281. case 0x05:
  282. mode = ApiPwm_ForceSet;
  283. break;
  284. case 0x06:
  285. mode = ApiPwm_HigherClear;
  286. break;
  287. case 0x07:
  288. mode = ApiPwm_HigherSet;
  289. break;
  290. default:
  291. mode = ApiPwm_NoAction;
  292. break;
  293. }
  294. return mode;
  295. }
  296. void iPwm_SetCompareMode(uint8_t devIndex, uint8_t channelIndex, ApiPwm_CompareMode mode)
  297. {
  298. uint32_t base = Pwms[devIndex].PwmBase;
  299. uint8_t conf = 0;
  300. switch (mode)
  301. {
  302. case ApiPwm_NoAction:
  303. conf = 0x00;
  304. break;
  305. case ApiPwm_UpMatchSet:
  306. conf = 0x01;
  307. break;
  308. case ApiPwm_UpMatchClear:
  309. conf = 0x02;
  310. break;
  311. case ApiPwm_UpMatchToggle:
  312. conf = 0x03;
  313. break;
  314. case ApiPwm_ForceClear:
  315. conf = 0x04;
  316. break;
  317. case ApiPwm_ForceSet:
  318. conf = 0x05;
  319. break;
  320. case ApiPwm_HigherClear:
  321. conf = 0x06;
  322. break;
  323. case ApiPwm_HigherSet:
  324. conf = 0x07;
  325. break;
  326. default:
  327. break;
  328. }
  329. #if API_FUNCTION_PWM_COUNTDOWN
  330. if (iPwm_GetCountMode(devIndex) == ApiPwm_CountDown)
  331. {
  332. switch (mode)
  333. {
  334. case ApiPwm_DownMatchSet:
  335. conf = 0x01;
  336. break;
  337. case ApiPwm_DownMatchClear:
  338. conf = 0x02;
  339. break;
  340. case ApiPwm_DownMatchToggle:
  341. conf = 0x03;
  342. break;
  343. }
  344. }
  345. #endif
  346. switch (channelIndex)
  347. {
  348. case 0:
  349. TIMER_CHCTL0(base) &= ~((uint32_t)0x000000F0UL);
  350. TIMER_CHCTL0(base) |= (((uint32_t)conf) << 4);
  351. break;
  352. case 1:
  353. TIMER_CHCTL0(base) &= ~((uint32_t)0x0000F000UL);
  354. TIMER_CHCTL0(base) |= (((uint32_t)conf) << (4 + 8));
  355. break;
  356. case 2:
  357. TIMER_CHCTL1(base) &= ~((uint32_t)0x000000F0UL);
  358. TIMER_CHCTL1(base) |= (((uint32_t)conf) << 4);
  359. break;
  360. case 3:
  361. TIMER_CHCTL1(base) &= ~((uint32_t)0x0000F000UL);
  362. TIMER_CHCTL1(base) |= (((uint32_t)conf) << (4 + 8));
  363. break;
  364. }
  365. }
  366. uint32_t iPwm_GetCompareValue(uint8_t devIndex, uint8_t channelIndex)
  367. {
  368. uint32_t base = Pwms[devIndex].PwmBase;
  369. uint32_t value = 0;
  370. switch (channelIndex)
  371. {
  372. case 0:
  373. value = TIMER_CH0CV(base);
  374. break;
  375. case 1:
  376. value = TIMER_CH1CV(base);
  377. break;
  378. case 2:
  379. value = TIMER_CH2CV(base);
  380. break;
  381. case 3:
  382. value = TIMER_CH3CV(base);
  383. break;
  384. default:
  385. break;
  386. }
  387. return value;
  388. }
  389. void iPwm_SetCompareValue(uint8_t devIndex, uint8_t channelIndex, uint32_t value)
  390. {
  391. ASSERT_LESS(devIndex, 1);
  392. ASSERT_LESS(channelIndex, 3);
  393. Pwms[devIndex].CompareValues[channelIndex] = value;
  394. }
  395. void iPwm_SetCompareValueDelay(uint8_t devIndex, uint8_t channelIndex, uint32_t value)
  396. {
  397. ASSERT_LESS(devIndex, 1);
  398. ASSERT_LESS(channelIndex, 3);
  399. Pwms[devIndex].CompareValues[channelIndex + 3] = value;
  400. }
  401. void iPwm_SetCompareGroupValues16(uint8_t devIndex, uint16_t* values)
  402. {
  403. for (int i = 0; i < 6; i++)
  404. {
  405. Pwms[devIndex].CompareValues[i] = values[i];
  406. }
  407. }
  408. void iPwm_SetCompareValueImmediate(uint8_t devIndex, uint8_t channelIndex, uint32_t value)
  409. {
  410. ASSERT_LESS(devIndex, 1);
  411. ASSERT_LESS(channelIndex, 4);
  412. uint32_t base = Pwms[devIndex].PwmBase;
  413. switch (channelIndex)
  414. {
  415. case 0:
  416. TIMER_CH0CV(base) = value;
  417. break;
  418. case 1:
  419. TIMER_CH1CV(base) = value;
  420. break;
  421. case 2:
  422. TIMER_CH2CV(base) = value;
  423. break;
  424. case 3:
  425. TIMER_CH3CV(base) = value;
  426. break;
  427. default:
  428. break;
  429. }
  430. }
  431. int8_t iPwm_GetEnableState(uint8_t devIndex)
  432. {
  433. ASSERT_LESS(devIndex, 1);
  434. return Pwms[devIndex].OutputEnable;
  435. }
  436. void iPwm_EnableOutput(uint8_t devIndex)
  437. {
  438. ASSERT_LESS(devIndex, 1);
  439. uint32_t base = Pwms[devIndex].PwmBase;
  440. TIMER_CCHP(base) |= (uint32_t)0x00008000UL;
  441. Pwms[devIndex].OutputEnable = 1;
  442. }
  443. void iPwm_DisableOutput(uint8_t devIndex)
  444. {
  445. ASSERT_LESS(devIndex, 1);
  446. uint32_t base = Pwms[devIndex].PwmBase;
  447. TIMER_CCHP(base) &= ~((uint32_t)0x00008000UL);
  448. Pwms[devIndex].OutputEnable = 0;
  449. }
  450. int8_t iPwm_GetChannelEnableState(uint8_t devIndex, uint8_t channelIndex)
  451. {
  452. }
  453. void iPwm_EnableChannelOutput(uint8_t devIndex, uint8_t channelIndex)
  454. {
  455. ASSERT_LESS(devIndex, 1);
  456. ////ASSERT_LESS(channelIndex, 4);
  457. uint32_t base = Pwms[devIndex].PwmBase;
  458. if (channelIndex < 64)
  459. {
  460. TIMER_CHCTL2(base)|= ((uint32_t)0x01) << (channelIndex * 4);
  461. }
  462. else
  463. {
  464. TIMER_CHCTL2(base)|= ((uint32_t)0x04) << ((channelIndex - 64) * 4);
  465. }
  466. }
  467. void iPwm_DisableChannelOutput(uint8_t devIndex, uint8_t channelIndex)
  468. {
  469. ASSERT_LESS(devIndex, 1);
  470. ////ASSERT_LESS(channelIndex, 4);
  471. uint32_t base = Pwms[devIndex].PwmBase;
  472. if (channelIndex < 64)
  473. {
  474. TIMER_CHCTL2(base)&= ~(((uint32_t)0x01) << (channelIndex * 4));
  475. }
  476. else
  477. {
  478. TIMER_CHCTL2(base) &= ~(((uint32_t)0x04) << ((channelIndex - 64) * 4));
  479. }
  480. }
  481. void iPwm_EnableDeviceInterrupt(uint8_t devIndex, ApiPwm_DeviceInterrupt interrupt)
  482. {
  483. ASSERT_LESS(devIndex, 1);
  484. switch (interrupt)
  485. {
  486. case ApiPwm_CountZeroInt:
  487. Pwms[devIndex].CountZeroISR.Enable = 1;
  488. break;
  489. case ApiPwm_CountMaxInt:
  490. Pwms[devIndex].CountMaxISR.Enable = 1;
  491. break;
  492. case ApiPwm_BreakInt:
  493. Pwms[devIndex].BreakISR.Enable = 1;
  494. break;
  495. default:
  496. break;
  497. }
  498. }
  499. void iPwm_DisableDeviceInterrupt(uint8_t devIndex, ApiPwm_DeviceInterrupt interrupt)
  500. {
  501. ASSERT_LESS(devIndex, 1);
  502. switch (interrupt)
  503. {
  504. case ApiPwm_CountZeroInt:
  505. Pwms[devIndex].CountZeroISR.Enable = 0;
  506. break;
  507. case ApiPwm_CountMaxInt:
  508. Pwms[devIndex].CountMaxISR.Enable = 0;
  509. break;
  510. case ApiPwm_BreakInt:
  511. Pwms[devIndex].BreakISR.Enable = 0;
  512. break;
  513. default:
  514. break;
  515. }
  516. }
  517. void iPwm_EnableChannelInterrupt(uint8_t devIndex, uint8_t channelIndex, ApiPwm_ChannelInterrupt interrupt)
  518. {
  519. ASSERT_LESS(devIndex, 1);
  520. ASSERT_LESS(channelIndex, 4);
  521. Pwms[devIndex].ChannelISR[channelIndex].Enable = 1;
  522. }
  523. void iPwm_DisableChannelInterrupt(uint8_t devIndex, uint8_t channelIndex, ApiPwm_ChannelInterrupt interrupt)
  524. {
  525. ASSERT_LESS(devIndex, 1);
  526. ASSERT_LESS(channelIndex, 4);
  527. Pwms[devIndex].ChannelISR[channelIndex].Enable = 0;
  528. }
  529. void iPwm_BindDeviceInterrupt(uint8_t devIndex, ApiPwm_DeviceInterrupt interrupt, void (*action)())
  530. {
  531. ASSERT_LESS(devIndex, 1);
  532. switch (interrupt)
  533. {
  534. case ApiPwm_CountZeroInt:
  535. Pwms[devIndex].CountZeroISR.Action = action;
  536. break;
  537. case ApiPwm_CountMaxInt:
  538. Pwms[devIndex].CountMaxISR.Action = action;
  539. break;
  540. case ApiPwm_BreakInt:
  541. Pwms[devIndex].BreakISR.Action = action;
  542. break;
  543. default:
  544. break;
  545. }
  546. }
  547. void iPwm_BindChannelInterrupt(uint8_t devIndex, uint8_t channelIndex, ApiPwm_DeviceInterrupt interrupt, void (*action)())
  548. {
  549. ASSERT_LESS(devIndex, 1);
  550. ASSERT_LESS(channelIndex, 4);
  551. Pwms[devIndex].ChannelISR[channelIndex].Action = action;
  552. }
  553. int8_t iPwm_GetBreakState(uint8_t devIndex)
  554. {
  555. ASSERT_LESS(devIndex, 1);
  556. uint32_t base = Pwms[devIndex].PwmBase;
  557. return (TIMER_INTF(base) & ((uint32_t)0x00000080UL)) ? 1 : 0;
  558. }
  559. void iPwm_ClearBreak(uint8_t devIndex)
  560. {
  561. ASSERT_LESS(devIndex, 1);
  562. uint32_t base = Pwms[devIndex].PwmBase;
  563. TIMER_INTF(base) &= ~((uint32_t)0x00000080UL);
  564. }
  565. #if API_FUNCTION_PWM_SYNC_MULTI_SAMPLING
  566. void iPwm_EnableSyncMultiSampling(uint8_t devIndex)
  567. {
  568. Pwms[devIndex].SyncSamplingEnable = 1;
  569. }
  570. void iPwm_DisableSyncMultiSampling(uint8_t devIndex)
  571. {
  572. Pwms[devIndex].SyncSamplingEnable = 0;
  573. Pwms[devIndex].SyncSamplingUpTickCount = 1;
  574. Pwms[devIndex].SyncSamplingUpTick[0] = TIMER_CAR(Pwms[devIndex].PwmBase)>> 1;
  575. Pwms[devIndex].SyncSamplingDownTickCount = 1;
  576. Pwms[devIndex].SyncSamplingDownTick[0] = TIMER_CAR(Pwms[devIndex].PwmBase)>> 1;
  577. }
  578. void iPwm_SyncMultiSamplingCountUp(uint8_t devIndex, uint32_t samplingTicks[], uint8_t samplingCounts)
  579. {
  580. if (Pwms[devIndex].SyncSamplingEnable == 1)
  581. {
  582. Pwms[devIndex].SyncSamplingUpTickCount = samplingCounts;
  583. for (int i = 0; i < samplingCounts; i++)
  584. {
  585. Pwms[devIndex].SyncSamplingUpTick[i] = samplingTicks[i];
  586. }
  587. }
  588. }
  589. void iPwm_SyncMultiSamplingCountDown(uint8_t devIndex, uint32_t samplingTicks[], uint8_t samplingCounts)
  590. {
  591. if (Pwms[devIndex].SyncSamplingEnable == 1)
  592. {
  593. Pwms[devIndex].SyncSamplingDownTickCount = samplingCounts;
  594. for (int i = 0; i < samplingCounts; i++)
  595. {
  596. Pwms[devIndex].SyncSamplingDownTick[i] = samplingTicks[i];
  597. }
  598. }
  599. }
  600. #endif