motor_ctl-4/MSTLibraries/SelfTestLib/inc/STLparam.h

/**
  ******************************************************************************
  * @file STLparam.h 
  * @author  MCD Application Team
  * @version  V1.0.0
  * @date  May-2012
  * @brief  This file contains the parameters to be customized for
  *                      the final application.
  ******************************************************************************
  * @copyright
  *
  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
  *
  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  * You may not use this file except in compliance with the License.
  * You may obtain a copy of the License at:
  *
  *        http://www.st.com/software_license_agreement_liberty_v2
  *
  * Unless required by applicable law or agreed to in writing, software 
  * distributed under the License is distributed on an "AS IS" BASIS, 
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */ 

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __SELFTEST_PARAM_H
#define __SELFTEST_PARAM_H

/* Includes ------------------------------------------------------------------*/
#include "gd32f30x.h"

/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/

/* Exported types ------------------------------------------------------------*/
typedef enum {
              TEST_RUNNING,
              CLASS_B_DATA_FAIL,
              CTRL_FLW_ERROR,
              TEST_FAILURE,
              TEST_OK
              } ClassBTestStatus;
/* This is for having self-diagnostic messages reported on a PC via UART */
//#define STL_VERBOSE_POR       /* During Power-on phase only */
//#define STL_VERBOSE           /* During main program execution */


/* comment out next lines to remove any eval board control */
//#define STL_EVAL_MODE //ly

/* uncomment next line to use March-X test instead of March-C */
#define USE_MARCHX_RAM_TEST
#define USE_MARCH_X

/* uncomment next lines to configure proper watchdog control at run mode */
#define USE_INDEPENDENT_WDOG
/* #define USE_WINDOW_AT_INDEPENDENT_WDOG */
//#define USE_WINDOW_WDOG //ly

/* uncomment next lines to generate reset at fail safe routine */
#define GENERATE_RESET_AT_FAIL_SAFE

/* These are the direct and inverted data (pattern) used during the RAM
test, performed using March C- Algorithm */
#define BCKGRND     ((uint32_t)0x00000000uL)
#define INV_BCKGRND ((uint32_t)0xFFFFFFFFuL)

/* Initial value of the CRC */
#define CRC_INIT ((uint32_t)0x00000000uL)

/* Define the time bases for clock frequency measure: RUN and START time bases
must be equal or multiple. RUN time base must take into account SysTick
prescaler and PLL setting (if enabled) */
#define SYSTICK_2_ms_HSI ((uint32_t)16000uL) /* HSI = 8MHz */
#define SYSTICK_2_ms_HSE ((uint32_t)16000uL) /* HSE = 8MHz */

#define SYSTICK_1_ms_PLL ((uint32_t)72000) /* PLL = 72MHz, SysTick clock not prescaled */


#define SYSTICK_TB_START  ((uint32_t)SYSTICK_1_ms_PLL)
#define SYSTICK_TB_RUN  ((uint32_t)SYSTICK_1_ms_PLL)

/* This is to provide a time base longer than the SysTick for the main */
/* For instance this is needed to refresh the LSI watchdog and window watchdog */
#define SYSTICK_20ms_TB  ((uint32_t)10uL) /* 10*2ms */

/* Timeout required to avoid being stuck in while loops during clock circuitry
initialization, in case of problem. Watchdog is also active, but these timeouts
allow to react more quickly */
#define LSI_START_TIMEOUT ((uint32_t)1000uL) /* ~3.5ms (IAR, speed optimized) */

/* ~35ms to be adapted depending on crystal/resonator */
#define HSE_START_TIMEOUT ((uint32_t)10000uL)

/* For clock switch:~3.5ms (IAR, speed optimized) valid for 8MHz and 64MHz
(~3.5/8=450µs)*/
#define CLOCK_SWITCH_TIMEOUT ((uint32_t)1000uL)

/* PLL lock Timeout set to ~10ms (IAR, speed optimized) */
#define PLL_LOCK_TIMEOUT ((uint32_t)3000uL)

/* Value of the Internal oscillator in Hz*/
#define HSI_Freq    ((uint32_t)8000000uL)

/* HSE frequency above this limit considered as harmonics*/
#define HSE_LimitHigh ((uint32_t)(HSE_VALUE*5u)/4u) /* (HSEValue + 25%) */

/* HSE frequency below this limit considered as sub-harmonics*/
#define HSE_LimitLow ((uint32_t)(HSE_VALUE*3u)/4u)  /* (HSEValue - 25%) */

/* define the maximum U32 */
#define U32_MAX    ((uint32_t)4294967295uL)
#define REF_CRC16 ((uint16_t )(0x08007FF0))//ly add

/* -------------------------------------------------------------------------- */
/* ------------------ CONTROL FLOW TAGS and CHECKPOINTS --------------------- */
/* -------------------------------------------------------------------------- */
/* RAM_TEST_CALLEE is only needed for CtrlFlowCntInv when exiting routine */
/* This is because the RAM test routines destroys the control flow counters */
#define RAM_TEST_CALLEE         ((uint32_t)0xFFFFFFFFuL)

#define CPU_TEST_CALLER         ((uint32_t)2)
#define CPU_TEST_CALLEE         ((uint32_t)3) /* Do not modify: hard coded in assembly file */
#define WDG_TEST_CALLER         ((uint32_t)5)
#define CRC32_INIT_CALLEE       ((uint32_t)7)
#define CRC32_TEST_CALLER       ((uint32_t)11)
#define CRC32_TEST_CALLEE       ((uint32_t)13)
#define CRC_TEST_CALLER         ((uint32_t)17)
#define CRC16_TEST_CALLEE       ((uint32_t)19)
#define CLOCK_TEST_CALLER       ((uint32_t)23)
#define CLOCK_TEST_CALLEE       ((uint32_t)29)
#define LSI_INIT_CALLEE         ((uint32_t)31)
#define HSE_INIT_CALLEE         ((uint32_t)37)
#define RTC_INIT_CALLEE         ((uint32_t)41)
#define SYSTICK_INIT_CALLEE     ((uint32_t)43)
#define CLOCK_SWITCH_CALLEE     ((uint32_t)47)
#define STACK_OVERFLOW_TEST     ((uint32_t)53)
#define STACK_OVERFLOW_CALLEE   ((uint32_t)59)
#define CLOCKPERIOD_TEST_CALLEE ((uint32_t)61)
#define CRC16_RUN_TEST_CALLEE   ((uint32_t)67)
#define CRC32_RUN_TEST_CALLEE   ((uint32_t)71)
#define FLASH_TEST_CALLER       ((uint32_t)73)
#define ADC_TEST_CALLER       ((uint32_t)77)


#ifdef __IAR_SYSTEMS_ICC__ /* IAR Compiler */
  #define CHECKPOINT1 ((uint32_t)CPU_TEST_CALLER + \
                          /* CPU_TEST_CALLEE */0 + \
                         /* WDG_TEST_CALLER */0 + \
                          CRC32_INIT_CALLEE + \
                          CRC32_TEST_CALLER + \
                          CRC_TEST_CALLER)
#endif /* __IAR_SYSTEMS_ICC__ */

#ifdef __CC_ARM   /* KEIL Compiler */
  #define CHECKPOINT1 ((uint32_t)CPU_TEST_CALLER + \
                          CPU_TEST_CALLEE + \
                          WDG_TEST_CALLER + \
                          CRC32_TEST_CALLER + \
                          CRC32_INIT_CALLEE + \
                          CRC_TEST_CALLER + \
                          CRC16_TEST_CALLEE)
#endif /* __CC_ARM */

#define CHECKPOINT2 ((uint32_t)CLOCK_TEST_CALLER + \
                          CLOCK_TEST_CALLEE + \
                          LSI_INIT_CALLEE + \
                          /*HSE_INIT_CALLEE*/0 + \
                          RTC_INIT_CALLEE + \
                          SYSTICK_INIT_CALLEE + \
                          /*CLOCK_SWITCH_CALLEE*/0 + \
                          STACK_OVERFLOW_TEST)

/* This is for run-time tests with 16-bit CRC */
#define DELTA_MAIN  ((uint32_t)CPU_TEST_CALLER + \
                          /*CPU_TEST_CALLEE*/0 + \
                          STACK_OVERFLOW_TEST + \
                          STACK_OVERFLOW_CALLEE + \
                          CLOCK_TEST_CALLER + \
                          CLOCK_TEST_CALLEE + \
                          /*CLOCKPERIOD_TEST_CALLEE*/0 + \
                          FLASH_TEST_CALLER + \
                          CRC32_RUN_TEST_CALLEE + \
                          CRC32_TEST_CALLEE + \
                          ADC_TEST_CALLER)

#define LAST_DELTA_MAIN ((uint32_t) DELTA_MAIN - CRC32_TEST_CALLEE + CRC32_INIT_CALLEE)
#define FULL_FLASH_CHECKED ((uint32_t)DELTA_MAIN * STEPS_NUMBER + LAST_DELTA_MAIN)

#define MEASPERIOD_ISR_CALLER   ((uint32_t)2)
#define MEASPERIOD_ISR_CALLEE   ((uint32_t)3)
#define CLOCKPERIOD_ISR_CALLEE  ((uint32_t)5)
#define RAM_MARCHC_ISR_CALLER   ((uint32_t)7)
#define RAM_MARCHC_ISR_CALLEE   ((uint32_t)11)
#define RAM_MARCHX_ISR_CALLER   ((uint32_t)13)
#define RAM_MARCHX_ISR_CALLEE   ((uint32_t)17)

#ifndef USE_MARCH_X
/* This is for March C tests */
#define DELTA_ISR  ((uint32_t)  /*MEASPERIOD_ISR_CALLER*/0 + \
                           RAM_MARCHC_ISR_CALLER + \
                           RAM_MARCHC_ISR_CALLEE)
#else
/* This is for March X tests */
#define DELTA_ISR  ((uint32_t)  /*MEASPERIOD_ISR_CALLER*/0+\
                              /*MEASPERIOD_ISR_CALLER*/0+\
                             /*CPU_TEST_CALLER +*/0+\
                           /*CPU_TEST_CALLEE*/0 + \
                           RAM_MARCHX_ISR_CALLER + \
                           RAM_MARCHX_ISR_CALLEE) 
#endif /* USE_MARCH_X */
#define CLASS_B_ROWS (((uint32_t)RAM_END - (uint32_t)RAM_START+1) / 4u)
/* +1 below is for buffer self-test*/
#define RAM_TEST_COMPLETED ((uint32_t)(DELTA_ISR * (CLASS_B_ROWS-1)))//(CLASS_B_ROWS + 1u)))//(16*1024-8)/4

/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
#ifdef __IAR_SYSTEMS_ICC__  /* IAR Compiler */
/* This is the IAR compiler entry point, usually executed right after reset */
  extern void __iar_program_start( void );
  extern void Reset_Handler( void );
  extern uint16_t __checksum;
/* The 4 variables here above are set by IAR linker */
  extern uint32_t __ICFEDIT_region_ROM_start__;
  extern uint32_t __ICFEDIT_region_CLASSB_ROM_start__;
  extern uint32_t __ICFEDIT_region_ROM_end__;
  extern uint32_t __ICFEDIT_region_RAM_start__;
  extern uint32_t __ICFEDIT_region_RAM_end__;
  extern uint32_t __ICFEDIT_region_CLASSB_start__;
  extern uint32_t __ICFEDIT_region_CLASSB_end__; 
  extern uint32_t __ICFEDIT_region_PNT_start__;
  extern uint32_t __ICFEDIT_region_BUF_start__;

  /* Constants necessary for Flash CRC calculation  (last block - 64 bytes - separated for CRC) */
  #define ROM_START ((uint8_t *)(&__ICFEDIT_region_ROM_start__))
  #define ROM_END   ((uint8_t *)0x0803DFEF)    //((uint32_t *)(&__ICFEDIT_region_ROM_end__))
  #define ROM_SIZE  (0x0803DFEF - 0x08003000 + 1u)

  #define STEPS_NUMBER          ((uint32_t)ROM_SIZE / 16u)//64u)
  #define ROM_SIZEinWORDS       (uint32_t) (ROM_SIZE / 4u)
  #define FLASH_BLOCK           (uint32_t)((ROM_SIZE) / STEPS_NUMBER)
  #define FLASH_BLOCK_WORDS     (uint32_t)((ROM_SIZEinWORDS) / STEPS_NUMBER)

  /* Constants necessary for RAM test (RAM_END is word aligned) */
  #define RAM_START   (uint32_t *)0x20000000
  

  #define RAM_END   (uint32_t *)0x20017FFF//0x2000BFFc

  
  /* Constants necessary for Transparent March tests */
  #define CLASS_B_START ((uint32_t *)(&__ICFEDIT_region_CLASSB_start__))
  #define CLASS_B_END ((uint32_t *)(&__ICFEDIT_region_CLASSB_end__))
  #define PNT_B_START ((uint32_t *)(&__ICFEDIT_region_PNT_start__ ))
  #define BUF_B_START ((uint32_t *)(&__ICFEDIT_region_BUF_start__ ))
  
  
  #define GotoCompilerStartUp() __iar_program_start();

  //#define REF_CRC32 __checksum
  #define REF_CRC32 ((uint32_t *)(0x0803DFF0))//__checksum

#endif  /* __IAR_SYSTEMS_ICC__ */

#ifdef __CC_ARM   /* KEIL Compiler */

  /* This is the KEIL compiler entry point, usually executed right after reset */
  extern void Reset_Handler( void ); 
  extern const uint32_t __Check_Sum;
  #define GotoCompilerStartUp() Reset_Handler();

  /* Constants necessary for Flash CRC calculation (ROM_SIZE in byte) */
	/* byte-aligned addresses */
  #define ROM_START ((uint8_t *)0x08000000)
  #define ROM_END   ((uint8_t *)(&__Check_Sum) - 1)
  #define ROM_SIZE  ((uint32_t)ROM_END - (uint32_t)ROM_START + 1)

  #define ROM_SIZEinWORDS (uint32_t) (ROM_SIZE/4u)
  #define STEPS_NUMBER          ((uint32_t)ROM_SIZE/64)
  #define FLASH_BLOCK           (uint16_t)((ROM_SIZE)/STEPS_NUMBER)
  #define FLASH_BLOCK_WORDS     (uint32_t)((ROM_SIZEinWORDS)/STEPS_NUMBER)


  /* Constants necessary for Transparent March tests */
  #define CLASS_B_START ((uint32_t *) 0x20000040)
  #define CLASS_B_END   ((uint32_t *) 0x200000C0)

  /* Constants necessary for RAM test (RAM_END is word aligned ) */
  #define RAM_START (uint32_t *)0x20000000
  
  #ifdef STM32F30X
    #define RAM_END   (uint32_t *)0x2000BFFc
  #else
    #if defined(STM32F37X) || defined(STM32F38X)
      #define RAM_END   (uint32_t *)0x20007FFc
    #endif
  #endif

#endif  /* __CC_ARM */

#endif /* __SELFTEST_PARAM_H */
/******************* (C) COPYRIGHT STMicroelectronics *****END OF FILE****/