gd32f30x_it.c 17 KB

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  1. /*!
  2. \file gd32f3x0_it.c
  3. \brief interrupt service routines
  4. */
  5. /*
  6. Copyright (C) 2017 GigaDevice
  7. 2017-06-06, V1.0.0, firmware for GD32F3x0
  8. */
  9. #include "gd32f30x_it.h"
  10. #include "user.h"
  11. #include "TimeTask_Event.h"
  12. #include "syspar.h"
  13. #include "can.h"
  14. extern uint8_t data;
  15. /*!
  16. \brief this function handles NMI exception
  17. \param[in] none
  18. \param[out] none
  19. \retval none
  20. */
  21. void NMI_Handler(void)
  22. {
  23. }
  24. /*!
  25. \brief this function handles HardFault exception
  26. \param[in] none
  27. \param[out] none
  28. \retval none
  29. */
  30. void HardFault_Handler(void)
  31. {
  32. hw_blPWMOnFlg = TRUE;/* HardFault_Handler无法被屏蔽,hw_blPWMOnFlg可能被RAMtest修改 */
  33. hw_voPWMOff();
  34. /* if Hard Fault exception occurs, go to infinite loop */
  35. while (1);
  36. }
  37. /*!
  38. \brief this function handles MemManage exception
  39. \param[in] none
  40. \param[out] none
  41. \retval none
  42. */
  43. void MemManage_Handler(void)
  44. {
  45. /* if Memory Manage exception occurs, go to infinite loop */
  46. while (1);
  47. }
  48. /*!
  49. \brief this function handles BusFault exception
  50. \param[in] none
  51. \param[out] none
  52. \retval none
  53. */
  54. void BusFault_Handler(void)
  55. {
  56. /* if Bus Fault exception occurs, go to infinite loop */
  57. while (1);
  58. }
  59. /*!
  60. \brief this function handles UsageFault exception
  61. \param[in] none
  62. \param[out] none
  63. \retval none
  64. */
  65. void UsageFault_Handler(void)
  66. {
  67. /* if Usage Fault exception occurs, go to infinite loop */
  68. while (1);
  69. }
  70. /*!
  71. \brief this function handles SVC exception
  72. \param[in] none
  73. \param[out] none
  74. \retval none
  75. */
  76. void SVC_Handler(void)
  77. {
  78. }
  79. /*!
  80. \brief this function handles DebugMon exception
  81. \param[in] none
  82. \param[out] none
  83. \retval none
  84. */
  85. void DebugMon_Handler(void)
  86. {
  87. }
  88. /*!
  89. \brief this function handles PendSV exception
  90. \param[in] none
  91. \param[out] none
  92. \retval none
  93. */
  94. void PendSV_Handler(void)
  95. {
  96. }
  97. /*!
  98. \brief this function handles SysTick exception
  99. \param[in] none
  100. \param[out] none
  101. \retval none
  102. */
  103. void SysTick_Handler(void)
  104. {
  105. /* Add your code below */
  106. clas_ubSystickFlg = 1; // for TUV
  107. cp_ulSystickCnt ++;
  108. stl_voSystickProc();
  109. /* TBT interrupt */
  110. tbt_voIsr();
  111. /* UART Timeout */
  112. UART_voApplTimer();
  113. }
  114. /*!
  115. \brief
  116. \param[in] none
  117. \param[out] none
  118. \retval none
  119. */
  120. void ADC0_1_IRQHandler(void)
  121. {
  122. clasB_uwADCCnt++;
  123. if(cp_stFlg.CurrentSampleModelSelect == SINGLERESISITANCE)
  124. {
  125. static UWORD SampleTrigCount = 0;
  126. if (adc_flag_get(ADC1 , ADC_INT_FLAG_EOIC))
  127. {
  128. switch (SampleTrigCount)
  129. {
  130. /* Get the first current sample and set the sencond Trig time*/
  131. case 0:
  132. SampleTrigCount = 1;
  133. adc_uwADDMAPhase1 = ADC_IDATA0(ADC1);
  134. timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_3, pwm_stGenOut.uwSecondTrigCOMPR);
  135. break;
  136. /* Get the second current sample and set the first Trig time*/
  137. case 1:
  138. SampleTrigCount = 0;
  139. adc_uwADDMAPhase2 = ADC_IDATA0(ADC1);
  140. adc_disable(ADC1);
  141. //ADC_StopInjectedConversion(ADC2);
  142. break;
  143. default:
  144. SampleTrigCount = 0;
  145. break;
  146. }
  147. /* Clear the ADC interrupt flag */
  148. adc_interrupt_flag_clear(ADC1 , ADC_INT_FLAG_EOIC);
  149. }
  150. }
  151. else if(cp_stFlg.CurrentSampleModelSelect == RDSON)
  152. {
  153. if (adc_flag_get(ADC0, ADC_INT_FLAG_EOIC))
  154. {
  155. if ((TIMER_CTL0(TIMER0) & TIMER_CTL0_DIR) == 0)
  156. {
  157. adc_uwRdsonUReg = ADC_IDATA0(ADC0);
  158. adc_uwRdsonVReg = ADC_IDATA1(ADC0);
  159. adc_uwRdsonWReg = ADC_IDATA2(ADC0);
  160. timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_3, pwm_stGenOut.uwRDSONTrig);
  161. }
  162. adc_interrupt_flag_clear(ADC0 , ADC_INT_FLAG_EOIC);
  163. }
  164. }
  165. else if(cp_stFlg.CurrentSampleModelSelect == COMBINATION)
  166. {
  167. if (adc_flag_get(ADC0, ADC_INT_FLAG_EOIC))
  168. {
  169. //GPIO_OCTL(GPIOC) |= 0x0800; //TEST PC10
  170. if ((TIMER_CTL0(TIMER0) & TIMER_CTL0_DIR) == 0)
  171. {
  172. adc_uwRdsonUReg = ADC_IDATA0(ADC0);
  173. adc_uwRdsonVReg = ADC_IDATA1(ADC0);
  174. adc_uwRdsonWReg = ADC_IDATA2(ADC0);
  175. /* CH3 set to Frozen */
  176. TIMER_CHCTL1(TIMER0) &= ~0x7000;
  177. /* CH3 set to PWMMODE0 */
  178. TIMER_CHCTL1(TIMER0) |= 0x6000;
  179. }
  180. adc_interrupt_flag_clear(ADC0 , ADC_INT_FLAG_EOIC);
  181. //GPIO_OCTL(GPIOC) &= ~0x0800; //TEST PC10
  182. }
  183. if (adc_flag_get(ADC1, ADC_INT_FLAG_EOIC))
  184. {
  185. //GPIO_OCTL(GPIOC) |= 0x0400; //TEST PC11
  186. if ((TIMER_CTL0(TIMER0) & TIMER_CTL0_DIR) != 0)
  187. {
  188. if (pwm_stGenOut.blSampleCalibFlag == TRUE)
  189. {
  190. adc_uwADDMAPhase1 = ADC_IDATA0(ADC1);
  191. }
  192. /* CH3 set to Frozen */
  193. TIMER_CHCTL1(TIMER0) &= ~0x7000;
  194. /* CH3 set to PWMMODE0 */
  195. TIMER_CHCTL1(TIMER0) |= 0x7000;
  196. adc_disable(ADC1);
  197. }
  198. adc_interrupt_flag_clear(ADC1 , ADC_INT_FLAG_EOIC);
  199. //GPIO_OCTL(GPIOC) &= ~0x0400; //TEST PC11
  200. }
  201. }
  202. else
  203. {}
  204. }
  205. /*!
  206. \brief
  207. \param[in] none
  208. \param[out] none
  209. \retval none
  210. */
  211. UWORD tst_DMAStartCt = 0;
  212. UWORD tst_DMAStartFlag = 0;
  213. UWORD tmpSigTrigZ1 = 500;
  214. void TIMER0_UP_TIMER9_IRQHandler(void)
  215. {
  216. ///////////////
  217. clasB_uwTIM0Cnt ++;
  218. if(cp_stFlg.CurrentSampleModelSelect == SINGLERESISITANCE)
  219. {
  220. ULONG OVtimeCnt = 0;
  221. if(timer_interrupt_flag_get(TIMER0, TIMER_INT_FLAG_UP))
  222. {
  223. if((TIMER_CTL0(TIMER0) & TIMER_CTL0_DIR) == 0) // When Counting Up
  224. {
  225. /*Resolver lock data*/
  226. spi_voResolverLock();
  227. timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_3, pwm_stGenOut.uwFirstTrigCOMPR);
  228. /* TBC Up interrupt */
  229. tbc_voUpIsr();
  230. }
  231. else
  232. {
  233. TIMER_CNT(TIMER6) = 0;
  234. /* TBC Down interrupt */
  235. tbc_voDownIsr();
  236. while ((TIMER_CNT(TIMER6) < HW_PWM_PERIOD) && (OVtimeCnt < HW_HHPWM_PERIOD * FPWM_HZ))
  237. {
  238. OVtimeCnt++;
  239. };
  240. // ADC_StartInjectedConversion(ADC2);
  241. // ADC_StartConversion(ADC1);
  242. // ADC_StartConversion(ADC2);
  243. adc_enable(ADC1);
  244. adc_software_trigger_enable(ADC0, ADC_REGULAR_CHANNEL);
  245. /* Compara value load */
  246. hw_uwPWMCmpr[0] = pwm_stGenOut.uwNewTIM1COMPR[0];
  247. hw_uwPWMCmpr[1] = pwm_stGenOut.uwNewTIM1COMPR[1];
  248. hw_uwPWMCmpr[2] = pwm_stGenOut.uwNewTIM1COMPR[2];
  249. hw_uwPWMCmpr[3] = pwm_stGenOut.uwNewTIM1COMPR[3];
  250. hw_uwPWMCmpr[4] = pwm_stGenOut.uwNewTIM1COMPR[4];
  251. hw_uwPWMCmpr[5] = pwm_stGenOut.uwNewTIM1COMPR[5];
  252. timer_dma_enable(TIMER0,TIMER_DMA_UPD);
  253. dma_channel_enable(DMA0,DMA_CH4);
  254. }
  255. timer_interrupt_flag_clear(TIMER0, TIMER_INT_FLAG_UP);
  256. }
  257. }
  258. if(cp_stFlg.CurrentSampleModelSelect == RDSON)
  259. {
  260. ULONG OVtimeCnt = 0;
  261. if(timer_interrupt_flag_get(TIMER0, TIMER_INT_FLAG_UP))
  262. {
  263. if((TIMER_CTL0(TIMER0) & TIMER_CTL0_DIR) == 0) // When Counting Up
  264. {
  265. /*Resolver lock data*/
  266. spi_voResolverLock();
  267. adc_software_trigger_enable(ADC0, ADC_REGULAR_CHANNEL);
  268. tbc_voUpIsr();
  269. }
  270. else
  271. {
  272. TIMER_CNT(TIMER6) = 0;
  273. /* TBC Down interrupt */
  274. tbc_voDownIsr();
  275. while ((TIMER_CNT(TIMER6) < HW_PWM_PERIOD) && (OVtimeCnt < HW_HHPWM_PERIOD * FPWM_HZ))
  276. {
  277. OVtimeCnt++;
  278. };
  279. timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_3, pwm_stGenOut.uwRDSONTrig);
  280. /* Compara value load */
  281. hw_uwPWMCmpr[0] = pwm_stGenOut.uwNewTIM1COMPR[0];
  282. hw_uwPWMCmpr[1] = pwm_stGenOut.uwNewTIM1COMPR[1];
  283. hw_uwPWMCmpr[2] = pwm_stGenOut.uwNewTIM1COMPR[2];
  284. hw_uwPWMCmpr[3] = pwm_stGenOut.uwNewTIM1COMPR[3];
  285. hw_uwPWMCmpr[4] = pwm_stGenOut.uwNewTIM1COMPR[4];
  286. hw_uwPWMCmpr[5] = pwm_stGenOut.uwNewTIM1COMPR[5];
  287. timer_dma_enable(TIMER0,TIMER_DMA_UPD);
  288. dma_channel_enable(DMA0,DMA_CH4);
  289. }
  290. }
  291. timer_interrupt_flag_clear(TIMER0, TIMER_INT_FLAG_UP);
  292. }
  293. if(cp_stFlg.CurrentSampleModelSelect == COMBINATION)
  294. {
  295. ULONG OVtimeCnt = 0;
  296. if(timer_interrupt_flag_get(TIMER0, TIMER_INT_FLAG_UP))
  297. {
  298. if((TIMER_CTL0(TIMER0) & TIMER_CTL0_DIR) == 0) // When Counting Up
  299. {
  300. adc_enable(ADC0);
  301. // adc_interrupt_enable(ADC0 , ADC_INT_EOIC);
  302. //adc_external_trigger_config(ADC0, ADC_INSERTED_CHANNEL, ENABLE);
  303. /* Software trigger for regular sampling*/
  304. adc_software_trigger_enable(ADC0, ADC_REGULAR_CHANNEL);
  305. timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_3, pwm_stGenOut.uwRDSONTrig);
  306. /* TBC Up interrupt */
  307. tbc_voUpIsr();
  308. }
  309. else
  310. {
  311. adc_disable(ADC0);
  312. //adc_interrupt_disable(ADC0 , ADC_INT_EOIC);
  313. //adc_external_trigger_config(ADC0, ADC_INSERTED_CHANNEL, DISABLE);
  314. TIMER_CNT(TIMER6) = 0;
  315. /* TBC Down interrupt */
  316. tbc_voDownIsr();
  317. while ((TIMER_CNT(TIMER6) < HW_PWM_PERIOD) && (OVtimeCnt < HW_HHPWM_PERIOD * FPWM_HZ))
  318. {
  319. OVtimeCnt++;
  320. };
  321. /* ADC1 trigger for Ibus sampling*/
  322. adc_enable(ADC1);
  323. timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_3, tmpSigTrigZ1);
  324. tmpSigTrigZ1 = pwm_stGenOut.uwSigRTrig;
  325. /* Compara value load */
  326. hw_uwPWMCmpr[0] = pwm_stGenOut.uwNewTIM1COMPR[0];
  327. hw_uwPWMCmpr[1] = pwm_stGenOut.uwNewTIM1COMPR[1];
  328. hw_uwPWMCmpr[2] = pwm_stGenOut.uwNewTIM1COMPR[2];
  329. hw_uwPWMCmpr[3] = pwm_stGenOut.uwNewTIM1COMPR[3];
  330. hw_uwPWMCmpr[4] = pwm_stGenOut.uwNewTIM1COMPR[4];
  331. hw_uwPWMCmpr[5] = pwm_stGenOut.uwNewTIM1COMPR[5];
  332. timer_dma_enable(TIMER0,TIMER_DMA_UPD);
  333. dma_channel_enable(DMA0,DMA_CH4);
  334. }
  335. }
  336. timer_interrupt_flag_clear(TIMER0, TIMER_INT_FLAG_UP);
  337. }
  338. else
  339. {
  340. }
  341. }
  342. /*!
  343. \brief
  344. \param[in] none
  345. \param[out] none
  346. \retval none
  347. */
  348. void TIMER1_IRQHandler(void)
  349. {
  350. UWORD uwIntSource = 0;
  351. clasB_uwTIM1Cnt++;
  352. if (timer_interrupt_flag_get(TIMER1, TIMER_INT_FLAG_UP))
  353. {
  354. uwIntSource = 1;
  355. cadence_voCadenceCal(uwIntSource);
  356. bikespeed_voBikeSpeedCal(uwIntSource);
  357. timer_interrupt_flag_clear(TIMER1, TIMER_INT_FLAG_UP);
  358. }
  359. else if (timer_interrupt_flag_get(TIMER1, TIMER_INT_FLAG_CH2))
  360. {
  361. uwIntSource = 2;
  362. cadence_voCadenceCal(uwIntSource);
  363. if(gpio_input_bit_get(GPIOB, GPIO_PIN_10))
  364. {
  365. /* reset the CH2P and CH2NP bits */
  366. TIMER_CHCTL2(TIMER1) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP));
  367. TIMER_CHCTL2(TIMER1) |= (uint32_t)((uint32_t)(TIMER_IC_POLARITY_FALLING) << 8U);
  368. }
  369. else
  370. {
  371. /* reset the CH2P and CH2NP bits */
  372. TIMER_CHCTL2(TIMER1) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP));
  373. TIMER_CHCTL2(TIMER1) |= (uint32_t)((uint32_t)(TIMER_IC_POLARITY_RISING) << 8U);
  374. }
  375. timer_interrupt_flag_clear(TIMER1, TIMER_INT_FLAG_CH2);
  376. }
  377. else if (timer_interrupt_flag_get(TIMER1, TIMER_INT_FLAG_CH3))
  378. {
  379. uwIntSource = 3;
  380. bikespeed_voBikeSpeedCal(uwIntSource);
  381. timer_interrupt_flag_clear(TIMER1, TIMER_INT_FLAG_CH3);
  382. }
  383. }
  384. /*!
  385. \brief
  386. \param[in] none
  387. \param[out] none
  388. \retval none
  389. */
  390. void TIMER3_IRQHandler(void)
  391. {
  392. if(timer_interrupt_flag_get(TIMER3, TIMER_INT_FLAG_UP))
  393. {
  394. clasB_uwTIM3Cnt++;
  395. /* TBS interrupt */
  396. tbs_voIsr();
  397. timer_interrupt_flag_clear(TIMER3, TIMER_INT_FLAG_UP);
  398. }
  399. }
  400. /*!
  401. \brief
  402. \param[in] none
  403. \param[out] none
  404. \retval none
  405. */
  406. void TIMER5_IRQHandler(void)
  407. {
  408. if(timer_interrupt_flag_get(TIMER5, TIMER_INT_FLAG_UP))
  409. {
  410. clasB_uwTIM5Cnt++;
  411. TimingTaskTimerServer();
  412. /* Event_1ms interrupt */
  413. Event_1ms();
  414. timer_interrupt_flag_clear(TIMER5, TIMER_INT_FLAG_UP);
  415. }
  416. }
  417. /*!
  418. \brief
  419. \param[in] none
  420. \param[out] none
  421. \retval none
  422. */
  423. void USART0_IRQHandler(void)
  424. {
  425. }
  426. /*!
  427. \brief
  428. \param[in] none
  429. \param[out] none
  430. \retval none
  431. */
  432. void DMA1_Channel2_IRQHandler(void)
  433. {
  434. static UWORD uwTempCount = 0;
  435. // Read PC Conmand
  436. if (dma_flag_get(DMA1, DMA_CH2, DMA_INT_FLAG_FTF))
  437. {
  438. UART_voCBDoneRead(UART_ERR_OK, 22);
  439. DMA_CH2CTL(DMA1) &= ~DMA_CHXCTL_CHEN;
  440. //dma_flag_clear(DMA1, DMA_CH2, DMA_INT_FLAG_FTF);
  441. DMA_INTC(DMA1) |= DMA_FLAG_ADD(DMA_INT_FLAG_FTF, DMA_CH2);
  442. uwTempCount = 22 - DMA_CH2CNT(DMA1);
  443. DMA_CH2CNT(DMA1) = uwTempCount;
  444. DMA_CH2CTL(DMA1) |= DMA_CHXCTL_CHEN;
  445. }
  446. // RX error
  447. if (dma_flag_get(DMA1, DMA_CH2, DMA_FLAG_ERR))
  448. {
  449. DMA_CH2CTL(DMA1) &= ~DMA_CHXCTL_CHEN;
  450. //dma_flag_clear(DMA1, DMA_CH2, DMA_FLAG_ERR);
  451. DMA_INTC(DMA1) |= DMA_FLAG_ADD(DMA_FLAG_ERR, DMA_CH2);
  452. DMA_CH2CNT(DMA1) = 22;
  453. DMA_CH2CTL(DMA1) |= DMA_CHXCTL_CHEN;
  454. }
  455. }
  456. /*!
  457. \brief
  458. \param[in] none
  459. \param[out] none
  460. \retval none
  461. */
  462. void DMA1_Channel4_IRQHandler(void)
  463. {
  464. if (dma_flag_get(DMA1, DMA_CH4, DMA_INT_FLAG_FTF))
  465. {
  466. if (UART_stParaStatus.bParaStart)
  467. {
  468. UART_bInsertPendTx = FALSE; // clear insertBuffer pending
  469. UART_stParaStatus.bParaStart = FALSE; // clear parameter status
  470. }
  471. else
  472. {
  473. // do nothing
  474. }
  475. DMA_CH4CTL(DMA1) &= ~DMA_CHXCTL_CHEN;
  476. //dma_flag_clear(DMA1, DMA_CH4, DMA_INT_FLAG_FTF);
  477. DMA_INTC(DMA1) |= DMA_FLAG_ADD(DMA_INT_FLAG_FTF, DMA_CH4);
  478. UART_stParaStatus.bWriteBusy = FALSE;
  479. }
  480. // TX error
  481. if (dma_flag_get(DMA1, DMA_CH4, DMA_FLAG_ERR))
  482. {
  483. if (UART_stParaStatus.bParaStart)
  484. {
  485. UART_bInsertPendTx = FALSE; // clear insertBuffer pending
  486. UART_stParaStatus.bParaStart = FALSE; // clear parameter status
  487. }
  488. DMA_CH4CTL(DMA1) &= ~DMA_CHXCTL_CHEN;
  489. //dma_flag_clear(DMA1, DMA_CH4, DMA_FLAG_ERR);
  490. DMA_INTC(DMA1) |= DMA_FLAG_ADD(DMA_FLAG_ERR, DMA_CH4);
  491. UART_stParaStatus.bWriteBusy = FALSE;
  492. }
  493. }
  494. /*!
  495. \brief
  496. \param[in] none
  497. \param[out] none
  498. \retval none
  499. */
  500. UWORD uwCnts = 0;
  501. void CAN0_RX0_IRQHandler(void)
  502. {
  503. can_message_receive(CAN0, CAN_FIFO0, pRxMsg);
  504. if((pRxMsg->rx_ff != CAN_FF_STANDARD) || (pRxMsg->rx_dlen == 0))
  505. {
  506. can_interrupt_enable(CAN0, CAN_INT_RFF0);
  507. return;
  508. }
  509. switch (pRxMsg->rx_sfid)
  510. {
  511. case ID_PBU_BC:
  512. case ID_PBU_TO_MC: //鎺ユ敹PBU鏁版嵁
  513. {
  514. CAN_RxBuf_Struct_PBU.ucBufID = pRxMsg->rx_sfid;
  515. CAN_Rx_ISR(&CAN_RxBuf_Struct_PBU, pRxMsg->rx_dlen);
  516. break;
  517. }
  518. case ID_BMS_BC:
  519. case ID_BMS_TO_MC: //鎺ユ敹BMS鏁版嵁
  520. {
  521. CAN_RxBuf_Struct_BMS.ucBufID = pRxMsg->rx_sfid;
  522. CAN_Rx_ISR(&CAN_RxBuf_Struct_BMS, pRxMsg->rx_dlen);
  523. break;
  524. }
  525. case ID_HMI_BC:
  526. case ID_HMI_TO_MC: //鎺ユ敹HMI鏁版嵁
  527. {
  528. CAN_RxBuf_Struct_HMI.ucBufID = pRxMsg->rx_sfid;
  529. CAN_Rx_ISR(&CAN_RxBuf_Struct_HMI, pRxMsg->rx_dlen);
  530. break;
  531. }
  532. case ID_CDL_BC:
  533. case ID_CDL_TO_MC: // case ID_CDL_TO_MC_TE://鎺ユ敹CDL鏁版嵁
  534. {
  535. CAN_RxBuf_Struct_CDL.ucBufID = pRxMsg->rx_sfid;
  536. CAN_Rx_ISR(&CAN_RxBuf_Struct_CDL, pRxMsg->rx_dlen);
  537. break;
  538. }
  539. default:
  540. break;
  541. }
  542. can_interrupt_enable(CAN0, CAN_INT_RFF0);
  543. }
  544. void CAN0_RX1_IRQHandler(void)
  545. {
  546. }