gd32f30x_it.c 8.5 KB

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  1. /*!
  2. \file gd32f3x0_it.c
  3. \brief interrupt service routines
  4. */
  5. /*
  6. Copyright (C) 2022 GigaDevice
  7. 2022-12-01, V1.0.0, firmware for GD32F3x0
  8. */
  9. /******************************
  10. * Include File
  11. ******************************/
  12. #include "gd32f30x_it.h"
  13. #include "user.h"
  14. #include "TimeTask_Event.h"
  15. #include "can.h"
  16. #include "FSM_1st.h"
  17. #include "api_rt.h"
  18. /******************************
  19. * Parameter
  20. ******************************/
  21. extern uint8_t data;
  22. /******************************
  23. * Function
  24. ******************************/
  25. /*!
  26. \brief this function handles NMI exception
  27. \param[in] none
  28. \param[out] none
  29. \retval none
  30. */
  31. void NMI_Handler(void)
  32. {
  33. }
  34. /*!
  35. \brief this function handles HardFault exception
  36. \param[in] none
  37. \param[out] none
  38. \retval none
  39. */
  40. void HardFault_Handler(void)
  41. {
  42. hw_blPWMOnFlg = TRUE;/* HardFault_Handler无法被屏蔽,hw_blPWMOnFlg可能被RAMtest修改 */
  43. hw_voPWMOff();
  44. /* if Hard Fault exception occurs, go to infinite loop */
  45. while (1)
  46. {
  47. //do nothing
  48. }
  49. }
  50. /*!
  51. \brief this function handles MemManage exception
  52. \param[in] none
  53. \param[out] none
  54. \retval none
  55. */
  56. void MemManage_Handler(void)
  57. {
  58. /* if Memory Manage exception occurs, go to infinite loop */
  59. while (1)
  60. {
  61. //do nothing
  62. }
  63. }
  64. /*!
  65. \brief this function handles BusFault exception
  66. \param[in] none
  67. \param[out] none
  68. \retval none
  69. */
  70. void BusFault_Handler(void)
  71. {
  72. /* if Bus Fault exception occurs, go to infinite loop */
  73. while (1)
  74. {
  75. //do nothing
  76. }
  77. }
  78. /*!
  79. \brief this function handles UsageFault exception
  80. \param[in] none
  81. \param[out] none
  82. \retval none
  83. */
  84. void UsageFault_Handler(void)
  85. {
  86. /* if Usage Fault exception occurs, go to infinite loop */
  87. while (1)
  88. {
  89. //do nothing
  90. }
  91. }
  92. /*!
  93. \brief this function handles SVC exception
  94. \param[in] none
  95. \param[out] none
  96. \retval none
  97. */
  98. void SVC_Handler(void)
  99. {
  100. }
  101. /*!
  102. \brief this function handles DebugMon exception
  103. \param[in] none
  104. \param[out] none
  105. \retval none
  106. */
  107. void DebugMon_Handler(void)
  108. {
  109. }
  110. /*!
  111. \brief this function handles PendSV exception
  112. \param[in] none
  113. \param[out] none
  114. \retval none
  115. */
  116. void PendSV_Handler(void)
  117. {
  118. }
  119. /*!
  120. \brief this function handles SysTick exception
  121. \param[in] none
  122. \param[out] none
  123. \retval none
  124. */
  125. void SysTick_Handler(void)
  126. {
  127. iRtTimer_Isr(HW_SYSTICK_TIMER);
  128. }
  129. /*!
  130. \brief
  131. \param[in] none
  132. \param[out] none
  133. \retval none
  134. */
  135. void ADC0_1_IRQHandler(void)
  136. {
  137. /* MCU self check count */
  138. clasB_uwADCCnt++;
  139. iRtAdc_CompleteIsr(0);
  140. }
  141. /*!
  142. \brief
  143. \param[in] none
  144. \param[out] none
  145. \retval none
  146. */
  147. void TIMER0_UP_TIMER9_IRQHandler(void)
  148. {
  149. /* MCU self check count */
  150. clasB_uwTIM0Cnt ++;
  151. iRtPwm_UpdateIsr(0);
  152. }
  153. /*!
  154. \brief
  155. \param[in] none
  156. \param[out] none
  157. \retval none
  158. */
  159. void TIMER1_IRQHandler(void)
  160. {
  161. UWORD uwIntSource = 0;
  162. /* MCU self check count */
  163. clasB_uwTIM1Cnt++;
  164. if (timer_interrupt_flag_get(TIMER1, TIMER_INT_FLAG_UP) != 0)
  165. {
  166. if(switch_flg.SysCoef_Flag == TRUE)
  167. {
  168. uwIntSource = 1;
  169. cadence_voCadenceCal(uwIntSource);
  170. bikespeed_voBikeSpeedCal(uwIntSource);
  171. }
  172. timer_interrupt_flag_clear(TIMER1, TIMER_INT_FLAG_UP);
  173. }
  174. else if (timer_interrupt_flag_get(TIMER1, TIMER_INT_FLAG_CH2) != 0)
  175. {
  176. if(switch_flg.SysCoef_Flag == TRUE)
  177. {
  178. uwIntSource = 2;
  179. cadence_voCadenceCal(uwIntSource);
  180. /* Select rising or falling edge trigger */
  181. if(gpio_input_bit_get(GPIOB, GPIO_PIN_10) != 0)
  182. {
  183. /* reset the CH2P and CH2NP bits */
  184. TIMER_CHCTL2(TIMER1) &= ~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP);
  185. TIMER_CHCTL2(TIMER1) |= (uint32_t)((uint32_t)(TIMER_IC_POLARITY_FALLING) << 8U);
  186. }
  187. else
  188. {
  189. /* reset the CH2P and CH2NP bits */
  190. TIMER_CHCTL2(TIMER1) &= ~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP);
  191. TIMER_CHCTL2(TIMER1) |= (uint32_t)((uint32_t)(TIMER_IC_POLARITY_RISING) << 8U);
  192. }
  193. }
  194. timer_interrupt_flag_clear(TIMER1, TIMER_INT_FLAG_CH2);
  195. }
  196. else if (timer_interrupt_flag_get(TIMER1, TIMER_INT_FLAG_CH3) != 0)
  197. {
  198. if(switch_flg.SysCoef_Flag == TRUE)
  199. {
  200. uwIntSource = 3;
  201. bikespeed_voBikeSpeedCal(uwIntSource);
  202. }
  203. timer_interrupt_flag_clear(TIMER1, TIMER_INT_FLAG_CH3);
  204. }
  205. else
  206. {
  207. //do noting
  208. }
  209. }
  210. /*!
  211. \brief
  212. \param[in] none
  213. \param[out] none
  214. \retval none
  215. */
  216. void TIMER3_IRQHandler(void)
  217. {
  218. /* MCU self check count */
  219. clasB_uwTIM3Cnt++;
  220. iRtTimer_Isr(HW_TBS_TIMER);
  221. }
  222. /*!
  223. \brief
  224. \param[in] none
  225. \param[out] none
  226. \retval none
  227. */
  228. void TIMER5_IRQHandler(void)
  229. {
  230. /* MCU self check count */
  231. clasB_uwTIM5Cnt++;
  232. iRtTimer_Isr(HW_EVENT1MS_TIMER);
  233. }
  234. /*!
  235. \brief
  236. \param[in] none
  237. \param[out] none
  238. \retval none
  239. */
  240. void DMA1_Channel2_IRQHandler(void)
  241. {
  242. static UWORD uwTempCount = 0;
  243. /* Read PC Conmand */
  244. if (dma_flag_get(DMA1, DMA_CH2, DMA_INT_FLAG_FTF) != 0)
  245. {
  246. UART_voCBDoneRead(UART_ERR_OK, 22);
  247. DMA_CH2CTL(DMA1) &= ~DMA_CHXCTL_CHEN;
  248. //dma_flag_clear(DMA1, DMA_CH2, DMA_INT_FLAG_FTF);
  249. DMA_INTC(DMA1) |= DMA_FLAG_ADD(DMA_INT_FLAG_FTF, DMA_CH2);
  250. uwTempCount = 22 - DMA_CH2CNT(DMA1);
  251. DMA_CH2CNT(DMA1) = uwTempCount;
  252. DMA_CH2CTL(DMA1) |= DMA_CHXCTL_CHEN;
  253. }
  254. /* RX error */
  255. if (dma_flag_get(DMA1, DMA_CH2, DMA_FLAG_ERR) != 0)
  256. {
  257. DMA_CH2CTL(DMA1) &= ~DMA_CHXCTL_CHEN;
  258. //dma_flag_clear(DMA1, DMA_CH2, DMA_FLAG_ERR);
  259. DMA_INTC(DMA1) |= DMA_FLAG_ADD(DMA_FLAG_ERR, DMA_CH2);
  260. DMA_CH2CNT(DMA1) = 22;
  261. DMA_CH2CTL(DMA1) |= DMA_CHXCTL_CHEN;
  262. }
  263. }
  264. /*!
  265. \brief
  266. \param[in] none
  267. \param[out] none
  268. \retval none
  269. */
  270. void DMA1_Channel4_IRQHandler(void)
  271. {
  272. if (dma_flag_get(DMA1, DMA_CH4, DMA_INT_FLAG_FTF) != 0)
  273. {
  274. if (UART_stParaStatus.bParaStart)
  275. {
  276. UART_bInsertPendTx = FALSE; // clear insertBuffer pending
  277. UART_stParaStatus.bParaStart = FALSE; // clear parameter status
  278. }
  279. else
  280. {
  281. // do nothing
  282. }
  283. DMA_CH4CTL(DMA1) &= ~DMA_CHXCTL_CHEN;
  284. //dma_flag_clear(DMA1, DMA_CH4, DMA_INT_FLAG_FTF);
  285. DMA_INTC(DMA1) |= DMA_FLAG_ADD(DMA_INT_FLAG_FTF, DMA_CH4);
  286. UART_stParaStatus.bWriteBusy = FALSE;
  287. }
  288. /* TX error */
  289. if (dma_flag_get(DMA1, DMA_CH4, DMA_FLAG_ERR) != 0)
  290. {
  291. if (UART_stParaStatus.bParaStart)
  292. {
  293. UART_bInsertPendTx = FALSE; // clear insertBuffer pending
  294. UART_stParaStatus.bParaStart = FALSE; // clear parameter status
  295. }
  296. DMA_CH4CTL(DMA1) &= ~DMA_CHXCTL_CHEN;
  297. //dma_flag_clear(DMA1, DMA_CH4, DMA_FLAG_ERR);
  298. DMA_INTC(DMA1) |= DMA_FLAG_ADD(DMA_FLAG_ERR, DMA_CH4);
  299. UART_stParaStatus.bWriteBusy = FALSE;
  300. }
  301. }
  302. /*!
  303. \brief
  304. \param[in] none
  305. \param[out] none
  306. \retval none
  307. */
  308. void CAN0_RX0_IRQHandler(void)
  309. {
  310. can_message_receive(CAN0, CAN_FIFO0, pRxMsg);
  311. if((pRxMsg->rx_ff != CAN_FF_STANDARD) || (pRxMsg->rx_dlen == 0))
  312. {
  313. can_interrupt_enable(CAN0, CAN_INT_RFF0);
  314. return;
  315. }
  316. switch (pRxMsg->rx_sfid)
  317. {
  318. case ID_PBU_BC:
  319. case ID_PBU_TO_MC: //接收PBU数据
  320. {
  321. CAN_RxBuf_Struct_PBU.ucBufID = (UWORD)pRxMsg->rx_sfid;
  322. CAN_Rx_ISR(&CAN_RxBuf_Struct_PBU, pRxMsg->rx_dlen);
  323. break;
  324. }
  325. case ID_BMS_BC:
  326. case ID_BMS_TO_MC: //接收BMS数据
  327. {
  328. CAN_RxBuf_Struct_BMS.ucBufID = (UWORD)pRxMsg->rx_sfid;
  329. CAN_Rx_ISR(&CAN_RxBuf_Struct_BMS, pRxMsg->rx_dlen);
  330. break;
  331. }
  332. case ID_HMI_BC:
  333. case ID_HMI_TO_MC: //接收HMI数据
  334. {
  335. CAN_RxBuf_Struct_HMI.ucBufID = (UWORD)pRxMsg->rx_sfid;
  336. CAN_Rx_ISR(&CAN_RxBuf_Struct_HMI, pRxMsg->rx_dlen);
  337. break;
  338. }
  339. case ID_CDL_BC:
  340. case ID_CDL_TO_MC: // case ID_CDL_TO_MC_TE://接收CDL数据
  341. {
  342. CAN_RxBuf_Struct_CDL.ucBufID = (UWORD)pRxMsg->rx_sfid;
  343. CAN_Rx_ISR(&CAN_RxBuf_Struct_CDL, pRxMsg->rx_dlen);
  344. break;
  345. }
  346. default:
  347. break;
  348. }
  349. can_interrupt_enable(CAN0, CAN_INT_RFF0);
  350. }