gd32f30x_it.c 12 KB

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  1. /*!
  2. \file gd32f3x0_it.c
  3. \brief interrupt service routines
  4. */
  5. /*
  6. Copyright (C) 2022 GigaDevice
  7. 2022-12-01, V1.0.0, firmware for GD32F3x0
  8. */
  9. /******************************
  10. * Include File
  11. ******************************/
  12. #include "gd32f30x_it.h"
  13. #include "user.h"
  14. #include "TimeTask_Event.h"
  15. #include "can.h"
  16. #include "FSM_1st.h"
  17. #include "api_rt.h"
  18. /******************************
  19. * Parameter
  20. ******************************/
  21. extern uint8_t data;
  22. /******************************
  23. * Function
  24. ******************************/
  25. /*!
  26. \brief this function handles NMI exception
  27. \param[in] none
  28. \param[out] none
  29. \retval none
  30. */
  31. void NMI_Handler(void)
  32. {
  33. }
  34. /*!
  35. \brief this function handles HardFault exception
  36. \param[in] none
  37. \param[out] none
  38. \retval none
  39. */
  40. void HardFault_Handler(void)
  41. {
  42. hw_blPWMOnFlg = TRUE;/* HardFault_Handler无法被屏蔽,hw_blPWMOnFlg可能被RAMtest修改 */
  43. hw_voPWMOff();
  44. /* if Hard Fault exception occurs, go to infinite loop */
  45. while (1)
  46. {
  47. //do nothing
  48. }
  49. }
  50. /*!
  51. \brief this function handles MemManage exception
  52. \param[in] none
  53. \param[out] none
  54. \retval none
  55. */
  56. void MemManage_Handler(void)
  57. {
  58. /* if Memory Manage exception occurs, go to infinite loop */
  59. while (1)
  60. {
  61. //do nothing
  62. }
  63. }
  64. /*!
  65. \brief this function handles BusFault exception
  66. \param[in] none
  67. \param[out] none
  68. \retval none
  69. */
  70. void BusFault_Handler(void)
  71. {
  72. /* if Bus Fault exception occurs, go to infinite loop */
  73. while (1)
  74. {
  75. //do nothing
  76. }
  77. }
  78. /*!
  79. \brief this function handles UsageFault exception
  80. \param[in] none
  81. \param[out] none
  82. \retval none
  83. */
  84. void UsageFault_Handler(void)
  85. {
  86. /* if Usage Fault exception occurs, go to infinite loop */
  87. while (1)
  88. {
  89. //do nothing
  90. }
  91. }
  92. /*!
  93. \brief this function handles SVC exception
  94. \param[in] none
  95. \param[out] none
  96. \retval none
  97. */
  98. void SVC_Handler(void)
  99. {
  100. }
  101. /*!
  102. \brief this function handles DebugMon exception
  103. \param[in] none
  104. \param[out] none
  105. \retval none
  106. */
  107. void DebugMon_Handler(void)
  108. {
  109. }
  110. /*!
  111. \brief this function handles PendSV exception
  112. \param[in] none
  113. \param[out] none
  114. \retval none
  115. */
  116. void PendSV_Handler(void)
  117. {
  118. }
  119. /*!
  120. \brief this function handles SysTick exception
  121. \param[in] none
  122. \param[out] none
  123. \retval none
  124. */
  125. void SysTick_Handler(void)
  126. {
  127. cp_ulSystickCnt ++;
  128. /* MCU Self Check*/
  129. clas_ubSystickFlg = 1;
  130. stl_voSystickProc();
  131. /* UART Timeout */
  132. UART_voApplTimer();
  133. /* TBT interrupt */
  134. //tbt_voIsr();
  135. }
  136. /*!
  137. \brief
  138. \param[in] none
  139. \param[out] none
  140. \retval none
  141. */
  142. void ADC0_1_IRQHandler(void)
  143. {
  144. /* MCU self check count */
  145. clasB_uwADCCnt++;
  146. if (cp_stFlg.CurrentSampleModelSelect == COMBINATION)
  147. {
  148. if (ADC_STAT(ADC0) & ADC_INT_FLAG_EOIC)
  149. {
  150. // adc_uwRdsonUReg = ADC_IDATA0(ADC0);
  151. // adc_uwRdsonVReg = ADC_IDATA1(ADC0);
  152. // adc_uwRdsonWReg = ADC_IDATA2(ADC0);
  153. Adcs[1].Results[HW_ADC_IA_CH] = ADC_IDATA0(ADC0);
  154. Adcs[1].Results[HW_ADC_IB_CH] = ADC_IDATA1(ADC0);
  155. Adcs[1].Results[HW_ADC_IC_CH] = ADC_IDATA2(ADC0);
  156. /* ADC0 disable */
  157. ADC_CTL1(ADC0) &= ~((uint32_t)ADC_CTL1_ADCON);
  158. /* ADC1 trigger set */
  159. TIMER_CH3CV(TIMER0) = (uint32_t) Pwms[0].SyncSamplingUpTick[0];//pwm_stGenOut.uwSigRTrig;
  160. /* ADC1 enable */
  161. ADC_CTL1(ADC1) |= (uint32_t)ADC_CTL1_ADCON;
  162. /* ADC0 interrupt flag clear */
  163. ADC_STAT(ADC0) &= ~((uint32_t)ADC_INT_FLAG_EOIC);
  164. }
  165. else if (ADC_STAT(ADC1) & ADC_INT_FLAG_EOIC)
  166. {
  167. if (pwm_stGenOut.blSampleCalibFlag == TRUE)
  168. {
  169. Adcs[2].Results[HW_ADC_IDC_CH] = ADC_IDATA0(ADC1);
  170. }
  171. /* ADC1 disable */
  172. ADC_CTL1(ADC1) &= ~((uint32_t)ADC_CTL1_ADCON);
  173. /* ADC1 interrupt flag clear */
  174. ADC_STAT(ADC1) &= ~((uint32_t)ADC_INT_FLAG_EOIC);
  175. }
  176. else
  177. {
  178. //do noting
  179. }
  180. }
  181. else
  182. {
  183. //do noting
  184. }
  185. }
  186. /*!
  187. \brief
  188. \param[in] none
  189. \param[out] none
  190. \retval none
  191. */
  192. void TIMER0_UP_TIMER9_IRQHandler(void)
  193. {
  194. ULONG ulOvTimeCnt = 0;
  195. /* MCU self check count */
  196. clasB_uwTIM0Cnt ++;
  197. if(cp_stFlg.CurrentSampleModelSelect == COMBINATION)
  198. {
  199. if(TIMER_INTF(TIMER0) & TIMER_INT_FLAG_UP)
  200. {
  201. if((TIMER_CTL0(TIMER0) & TIMER_CTL0_DIR) == 0) // When Counting Up
  202. {
  203. /* TBC Up interrupt */
  204. tbc_voUpIsr();
  205. }
  206. else
  207. {
  208. TIMER_CNT(TIMER6) = 0;
  209. /* TBC Down interrupt */
  210. tbc_voDownIsr();
  211. /* Timing management, refer to the Software design description for details */
  212. while ((TIMER_CNT(TIMER6) < HW_PWM_PERIOD) && (ulOvTimeCnt < 10000))
  213. {
  214. ulOvTimeCnt++;
  215. };
  216. /* ADC0 trigger set */
  217. TIMER_CH3CV(TIMER0) = (uint32_t) Pwms[0].SyncSamplingUpTick[1];
  218. /* ADC Enable*/
  219. iAdc_Enable(0);
  220. /* Software trigger for regular sampling*/
  221. iAdc_Convert(0);
  222. /* Compara value load */
  223. iRtPwm_ActivateCompareValues(0);
  224. timer_dma_enable(TIMER0,TIMER_DMA_UPD);
  225. dma_channel_enable(DMA0,DMA_CH4);
  226. }
  227. }
  228. /* Timer0 update interrupt flag clear */
  229. TIMER_INTF(TIMER0) = ~(uint32_t)TIMER_INT_FLAG_UP;
  230. }
  231. else
  232. {
  233. //do noting
  234. }
  235. }
  236. /*!
  237. \brief
  238. \param[in] none
  239. \param[out] none
  240. \retval none
  241. */
  242. void TIMER1_IRQHandler(void)
  243. {
  244. UWORD uwIntSource = 0;
  245. /* MCU self check count */
  246. clasB_uwTIM1Cnt++;
  247. if (timer_interrupt_flag_get(TIMER1, TIMER_INT_FLAG_UP) != 0)
  248. {
  249. if(switch_flg.SysCoef_Flag == TRUE)
  250. {
  251. uwIntSource = 1;
  252. cadence_voCadenceCal(uwIntSource);
  253. bikespeed_voBikeSpeedCal(uwIntSource);
  254. }
  255. timer_interrupt_flag_clear(TIMER1, TIMER_INT_FLAG_UP);
  256. }
  257. else if (timer_interrupt_flag_get(TIMER1, TIMER_INT_FLAG_CH2) != 0)
  258. {
  259. if(switch_flg.SysCoef_Flag == TRUE)
  260. {
  261. uwIntSource = 2;
  262. cadence_voCadenceCal(uwIntSource);
  263. /* Select rising or falling edge trigger */
  264. if(gpio_input_bit_get(GPIOB, GPIO_PIN_10) != 0)
  265. {
  266. /* reset the CH2P and CH2NP bits */
  267. TIMER_CHCTL2(TIMER1) &= ~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP);
  268. TIMER_CHCTL2(TIMER1) |= (uint32_t)((uint32_t)(TIMER_IC_POLARITY_FALLING) << 8U);
  269. }
  270. else
  271. {
  272. /* reset the CH2P and CH2NP bits */
  273. TIMER_CHCTL2(TIMER1) &= ~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP);
  274. TIMER_CHCTL2(TIMER1) |= (uint32_t)((uint32_t)(TIMER_IC_POLARITY_RISING) << 8U);
  275. }
  276. }
  277. timer_interrupt_flag_clear(TIMER1, TIMER_INT_FLAG_CH2);
  278. }
  279. else if (timer_interrupt_flag_get(TIMER1, TIMER_INT_FLAG_CH3) != 0)
  280. {
  281. if(switch_flg.SysCoef_Flag == TRUE)
  282. {
  283. uwIntSource = 3;
  284. bikespeed_voBikeSpeedCal(uwIntSource);
  285. }
  286. timer_interrupt_flag_clear(TIMER1, TIMER_INT_FLAG_CH3);
  287. }
  288. else
  289. {
  290. //do noting
  291. }
  292. }
  293. /*!
  294. \brief
  295. \param[in] none
  296. \param[out] none
  297. \retval none
  298. */
  299. void TIMER3_IRQHandler(void)
  300. {
  301. if(timer_interrupt_flag_get(TIMER3, TIMER_INT_FLAG_UP) != 0)
  302. {
  303. /* MCU self check count */
  304. clasB_uwTIM3Cnt++;
  305. /* TBS interrupt */
  306. tbs_voIsr();
  307. timer_interrupt_flag_clear(TIMER3, TIMER_INT_FLAG_UP);
  308. }
  309. }
  310. /*!
  311. \brief
  312. \param[in] none
  313. \param[out] none
  314. \retval none
  315. */
  316. void TIMER5_IRQHandler(void)
  317. {
  318. if(timer_interrupt_flag_get(TIMER5, TIMER_INT_FLAG_UP) != 0)
  319. {
  320. /* MCU self check count */
  321. clasB_uwTIM5Cnt++;
  322. /* Timing of time slices */
  323. TimingTaskTimerServer();
  324. /* Event_1ms interrupt */
  325. Event_1ms();
  326. timer_interrupt_flag_clear(TIMER5, TIMER_INT_FLAG_UP);
  327. }
  328. }
  329. /*!
  330. \brief
  331. \param[in] none
  332. \param[out] none
  333. \retval none
  334. */
  335. void DMA1_Channel2_IRQHandler(void)
  336. {
  337. static UWORD uwTempCount = 0;
  338. /* Read PC Conmand */
  339. if (dma_flag_get(DMA1, DMA_CH2, DMA_INT_FLAG_FTF) != 0)
  340. {
  341. UART_voCBDoneRead(UART_ERR_OK, 22);
  342. DMA_CH2CTL(DMA1) &= ~DMA_CHXCTL_CHEN;
  343. //dma_flag_clear(DMA1, DMA_CH2, DMA_INT_FLAG_FTF);
  344. DMA_INTC(DMA1) |= DMA_FLAG_ADD(DMA_INT_FLAG_FTF, DMA_CH2);
  345. uwTempCount = 22 - DMA_CH2CNT(DMA1);
  346. DMA_CH2CNT(DMA1) = uwTempCount;
  347. DMA_CH2CTL(DMA1) |= DMA_CHXCTL_CHEN;
  348. }
  349. /* RX error */
  350. if (dma_flag_get(DMA1, DMA_CH2, DMA_FLAG_ERR) != 0)
  351. {
  352. DMA_CH2CTL(DMA1) &= ~DMA_CHXCTL_CHEN;
  353. //dma_flag_clear(DMA1, DMA_CH2, DMA_FLAG_ERR);
  354. DMA_INTC(DMA1) |= DMA_FLAG_ADD(DMA_FLAG_ERR, DMA_CH2);
  355. DMA_CH2CNT(DMA1) = 22;
  356. DMA_CH2CTL(DMA1) |= DMA_CHXCTL_CHEN;
  357. }
  358. }
  359. /*!
  360. \brief
  361. \param[in] none
  362. \param[out] none
  363. \retval none
  364. */
  365. void DMA1_Channel4_IRQHandler(void)
  366. {
  367. if (dma_flag_get(DMA1, DMA_CH4, DMA_INT_FLAG_FTF) != 0)
  368. {
  369. if (UART_stParaStatus.bParaStart)
  370. {
  371. UART_bInsertPendTx = FALSE; // clear insertBuffer pending
  372. UART_stParaStatus.bParaStart = FALSE; // clear parameter status
  373. }
  374. else
  375. {
  376. // do nothing
  377. }
  378. DMA_CH4CTL(DMA1) &= ~DMA_CHXCTL_CHEN;
  379. //dma_flag_clear(DMA1, DMA_CH4, DMA_INT_FLAG_FTF);
  380. DMA_INTC(DMA1) |= DMA_FLAG_ADD(DMA_INT_FLAG_FTF, DMA_CH4);
  381. UART_stParaStatus.bWriteBusy = FALSE;
  382. }
  383. /* TX error */
  384. if (dma_flag_get(DMA1, DMA_CH4, DMA_FLAG_ERR) != 0)
  385. {
  386. if (UART_stParaStatus.bParaStart)
  387. {
  388. UART_bInsertPendTx = FALSE; // clear insertBuffer pending
  389. UART_stParaStatus.bParaStart = FALSE; // clear parameter status
  390. }
  391. DMA_CH4CTL(DMA1) &= ~DMA_CHXCTL_CHEN;
  392. //dma_flag_clear(DMA1, DMA_CH4, DMA_FLAG_ERR);
  393. DMA_INTC(DMA1) |= DMA_FLAG_ADD(DMA_FLAG_ERR, DMA_CH4);
  394. UART_stParaStatus.bWriteBusy = FALSE;
  395. }
  396. }
  397. /*!
  398. \brief
  399. \param[in] none
  400. \param[out] none
  401. \retval none
  402. */
  403. void CAN0_RX0_IRQHandler(void)
  404. {
  405. can_message_receive(CAN0, CAN_FIFO0, pRxMsg);
  406. if((pRxMsg->rx_ff != CAN_FF_STANDARD) || (pRxMsg->rx_dlen == 0))
  407. {
  408. can_interrupt_enable(CAN0, CAN_INT_RFF0);
  409. return;
  410. }
  411. switch (pRxMsg->rx_sfid)
  412. {
  413. case ID_PBU_BC:
  414. case ID_PBU_TO_MC: //接收PBU数据
  415. {
  416. CAN_RxBuf_Struct_PBU.ucBufID = (UWORD)pRxMsg->rx_sfid;
  417. CAN_Rx_ISR(&CAN_RxBuf_Struct_PBU, pRxMsg->rx_dlen);
  418. break;
  419. }
  420. case ID_BMS_BC:
  421. case ID_BMS_TO_MC: //接收BMS数据
  422. {
  423. CAN_RxBuf_Struct_BMS.ucBufID = (UWORD)pRxMsg->rx_sfid;
  424. CAN_Rx_ISR(&CAN_RxBuf_Struct_BMS, pRxMsg->rx_dlen);
  425. break;
  426. }
  427. case ID_HMI_BC:
  428. case ID_HMI_TO_MC: //接收HMI数据
  429. {
  430. CAN_RxBuf_Struct_HMI.ucBufID = (UWORD)pRxMsg->rx_sfid;
  431. CAN_Rx_ISR(&CAN_RxBuf_Struct_HMI, pRxMsg->rx_dlen);
  432. break;
  433. }
  434. case ID_CDL_BC:
  435. case ID_CDL_TO_MC: // case ID_CDL_TO_MC_TE://接收CDL数据
  436. {
  437. CAN_RxBuf_Struct_CDL.ucBufID = (UWORD)pRxMsg->rx_sfid;
  438. CAN_Rx_ISR(&CAN_RxBuf_Struct_CDL, pRxMsg->rx_dlen);
  439. break;
  440. }
  441. default:
  442. break;
  443. }
  444. can_interrupt_enable(CAN0, CAN_INT_RFF0);
  445. }